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Memory IP

Faraday's memory compilers provide designers with a variety of embedded memory in the form of reusable IP that facilitate ASIC and SoC designs.

All Faraday memory compilers are developed using custom memory design techniques following a dedicated streamline process to achieve industry-leading results in die size, speed, and power. All Faraday's memory compilers are configured using EDA tools, BIST codes, and parameterized by power ports, making them ideal for highly integrated chip applications.

Being a strategic partner of UMC foundry, Faraday's memory compilers are configured to port on UMC logic process. The figure below illustrates the full-range of memory IPs covering advance process technologies from 0.18£gm to 28nm:Faraday Memory Compiler Offerings


A list of Faraday's memory compiler process is shown below:

28nm

28nm HPM Memory Compilers

40nm

40nm LP Memory Compilers

55nm

55nm SP Memory Compilers

55nm LP Memory Compilers

65nm

65nm LP Memory Compilers

65nm SP Memory Compilers

65nm LL Memory Compilers

90nm

90nm SP Memory Compilers

0.11um

0.11um HS Al Advance Enhancement (110AE-HS) Memory Compilers

0.11um LL Al Advance Enhancement (110AE-LL) Memory Compilers

0.11um SP Al Advance Enhancement (110AE-SP) Memory Compilers

0.11um eFlash-LL Memory Compilers

0.11um HS Memory Compilers

0.11um LL Memory Compilers

0.13um

0.13um HS Memory Compilers

0.13um HS PowerSlash Memory Compilers

0.13um Fusion (HS+LL) Memory Compilers

0.13um LL Memory Compilers

0.13um SP Memory Compilers

0.15um

0.15um SP Memory Compilers

0.153um

0.153um Memory Compilers

0.18um

0.18um Memory Compilers

0.18um Low Leakage Memory Compilers

0.25um

0.25um Memory Compiler

0.35um

0.35um Memory Compiler