Faraday's miniIP ultra high-density and low-power IP platform is the industry's most complete IP solution delicately designed to help customers reduce both chip size and power consumption. The miniIP platform takes advantage of new architecture and circuit design techniques that enable designers to meet the growing needs for low cost and long battery life in the consumer electronics markets. In various users' ASIC projects, Faraday's miniIP platform has helped reduce 25%+ of chip size and 25% power consumption.
Faraday's miniIP Platform Portfolio
Faraday's miniIP portfolio is a collection of full-function essential IPs with drastically reduced area and power consumption:
miniLib™
Ultra high-density cell library with 20~30% reduction in core logic area and power consumption when compared with other standard cell libraries
miniIO™
High density general purpose I/Os with 40% reduction in the I/O area
POC™
Power-Over-Circuit technology which can reduce 5~10% of overall chip cost by moving the bonding pads above the I/O cells
miniROM™ Compiler
High-density diffusion programmable ROM generator which can gain 25% area reduction on the same configuration generated by via ROM compilers
miniViaROM™ Compiler
Ultra high-density and low-power Synchronous Via1 programmable ROM compiler
miniRAM™ Compiler
Ultra high-density and low-power single-port SRAM Compiler
miniPLL™
Essential component PLL completely integrated into the I/O region without taking any core area space
Pricing and Availability
Faraday's miniIP platform products are available in UMC 0.13um HS/SP/LL processes, and UMC 0.18um GII and LL processes. They are production proven and available for licensing immediately. The 0.13um and 0.18um miniLib and miniIO can be shrink to 0.11um and 0.162um to gain further area saving by request.
The license fee of miniLib starts from $100K with royalty, and package deals are available. Please check the product brief flyers for detailed pricing information, or contact Faraday sales and reps.
