Design Flow Enhancement on 28nm

As on-chip variation (OCV) effects continue to increase with shrinking geometry nodes, a single value derate has become overly pessimistic in most cases, and optimistic in others. Applying the worst-case variation across the entire chip has become less acceptable, due to overdesign, reduced design performance, and longer timing closure leadtime .

In order to apply realistic derate value, Faraday 28nm process adopts stage-based Advanced OCV (AOCV) method . Based on UMC global corner, AOCV table is characterized by Monte Carlo SPICE simulation, as the input to faraday timing signoff designkit - fstaH (Hyper).



Moreover, due to the expansion of signoff corners and timing analysis views, fstaH is equipped with ADMSA (Assigned and distributed multi-scenario analysis) and PBA (path-based analysis) that reduce the run time and minimize the pessimism respectively. In addition, fdrc (faraday design rule checker) applies frequency-rule-based slew/load check to guarantee accurate delay calculation with CCS model.

Derates for variances and simplified models often do over-guardbanding. Traditional SPICE simulation is a less practical approach for re-examination on whole critical paths of SOC. Faraday adopts 3rd part tool – pathFX as margin waive and relax tool, which the run time can be 300,000 times faster than SPICE. To see comprehensive Faraday 28nm flow, please contact faraday sales / FAE for more details.