IP

Faraday is one of the few leading ASIC vendors with a comprehensive self-developed IP portfolio. Its broad IP portfolio, ranging from 0.5µm to 28nm to meet different application requirements, includes fundamental libraries, memory compilers, high-speed I/O, DDR4, programmable SerDes, SoC related digital IP. These IPs help eliminate designers' integration risks and lower customers' IP licensing costs, which especially matter in today's complex ASIC and SoC design.

Faraday works in close collaboration with UMC, which allows the key IPs to be thoroughly validated as well as to be beneficial for stable mass productions and specific system requirements. 28nm HPC IPs have been subsumed into Faraday’s comprehensive IP portfolio and ready to bring the customers the benefits of high performance and low power-leakage.

Available 28nm HPC IP:

Standard Cell (Readiness):

Item
LVT
C40
LVT
C35
LVT
C30
RVT
C40
RVT
C35
RVT
C30
HVT
C40
HVT
C35
HVT
C30
7T
Base library
V
V
V
V
V
V
V
V
V
Power slash kit
-
V
-
-
V
-
-
V
-
ECO library
-
V
-
-
V
-
-
V
-
9T
Base library
V
V
V
V
V
V
V
V
V
Power slash kit
-
V
-
-
V
-
-
V
-
ECO library
-
V
-
-
V
-
-
V
-
12T
Base library
V
V
V
V
V
V
V
V
V
Power slash kit
-
V
-
-
V
-
-
V
-
ECO library
-
V
-
-
V
-
-
V
-
7T
(M1)
Base library
V
V
V
V
V
V
V
V
V
Power slash kit
-
V
-
-
V
-
-
V
-
ECO library
-
V
-
-
V
-
-
V
-
9T
(M1)
Base library
V
V
V
V
V
V
V
V
V
Power slash kit
-
V
-
-
V
-
-
V
-
ECO library
-
V
-
-
V
-
-
V
-
12T
(M1)
Base library
V
V
V
Power slash kit
-
V
-
-
V
-
-
-
ECO library
-
V
-
-
V
-
-
-

⊙ Under development; please contact Faraday for the detail.

 

Memory Compiler:

Feature
Readiness
SPRAM
V
1PRF
V
DPRAM
V
2PRF
V
VIA ROM
V
UHS 1PRF
V
UHS SPRAM
V
ULL SPRAM
V
ULL 1PRF
V
ULL DPRAM
V
ULL 2PRF
V
ULL VIA ROM
V
UHD SPRAM
V
UHD 1PRF
V

 

 

I/O Interface:

Feature
Readiness
GPIO (1.8V)
V
GPIO (1.8V/3.3V)
V
SSTL I/O (DDR4/3/3L/LPDDR3/LPDDR2 PHY)
V

 

 

HSIO:

Item
Feature
Readiness
SerDes PHY 1 ~ 12.5Gbps SerDes
V
MIPI D-PHY TX 80M~2.5Gbps
V
MIPI D-PHY RX 80M~2.5Gbps, Combo with LVDS,
sub-LVDS, HiSPi, COMS-in
V
80M~2.5Gbps
PCIe PHY G1/G2/G3
V
SATA PHY G1/G2/G3
1~12.5Gbps SerDes
V
USB PHY Pure 2.0, 480Mbps
V
USB 3.1 Gen 1, 5Gbps
V
USB 3.1, Gen 2, 10Gbps
V
Type-C (USB 3.1 Gen1, 5Gbps)
Type-C (USB 3.1 Gen2, 10Gbps)
V-by-One TX
4Gbps, 8-lane
V
V-by-One RX 4Gbps, 4-lane
V
LVDS TX 1.25Gbps
V
LVDS RX 1.25Gbps
V
Ethernet G-PHY
V
DDR PHY DDR4/3, LPDDR4/3
2.4Gbps
V
DDR4/3, LPDDR4/3
3.2Gbps
DDR4/3/3L, LPDDR3
2.4Gbps at DDR4
V

⊙ Under development; please contact Faraday for the detail.

 

Analog:

Item
Feature
Readiness
PLL Clock-in: 20M ~ 200MHz
Clock-out: 62.5M ~ 1GHz
V
Clock-in: 25M ~ 50MHz
Clock-out: 1000M ~ 2000MHz
V
Clock-in: 25M ~ 66MHz
Clock-out: 400M ~ 800MHz
V
Clock-in: 12MHz
Clock-out: 40M ~ 850MHz
V
Clock-in: 200M ~ 800MHz
Clock-out1: 200M ~ 800MHz
Clock-out2: 400M ~ 1600MHz
V
DLL Clock-in: 800M~1600MHz
Clock-out: 800M ~ 1600MHz
V
ADC 1.8V, 9bit, 125Msps pipelined ADC
DAC 1.8V, 10bit, 250Msps 3-ch Video DAC
Output Driver 3.3V
V
Audio Codec 24bit Stereo Audio Codec
V

⊙ Under development; please contact Faraday for the detail.