IP

IPs are the essential tools to help develop ICs for fast time-to-market. Faraday is one of the few leading ASIC vendors with a comprehensive self-developed IP portfolio.

Faraday's broad IP portfolio includes fundamental libraries, memory compilers, high-speed I/O, etc. These in-house developed IPs help eliminate designers' integration risks and lower customers' IP licensing costs, which especially matter in today's complex ASIC and SoC design. The 55ULP IPs also include Faraday’s PowerSlash™ IPs, which are the fundamental building blocks for a low-power design, including multi-Vt librariesand a comprehensive power management kit. The featured Turbo Mode effectively shifts the performance curve, helping MCU cores to achieve 2x performance or reduce dynamic power by 40% at nominal clock rates at UMC’s 55ULP process.

Silicon validation is the critical step to determine if the IP can be utilized for mass production. Faraday works in close collaboration with UMC, which allows the key IPs to be thoroughly validated as well as to be beneficial for stable mass productions and specific system requirements in the future.

Available 55nm ULP IP

Standard Cell (Readiness):

Item

LVT
C60
RVT
C60
HVT
C60
HVT
C90
HVT
C60
( PowerSlash™
with Turbo Mode)
HVT
C90
( PowerSlash™
with Turbo Mode)
uHVT
C90
( PowerSlash™
with Turbo Mode)
Note
6T Base library V V V V V V V  
Power slash kit V V V V - - -  
ECO library V V V V V V V  
8T Base library

V V V V V V V  
Power slash kit V V V V - - -  
ECO library V V V V V V V  
TGO
(RTC)
Base library - - V - - - - I/O device
  • Features:
    – 6/8 track high cell for high density and low power requirement
    – Up to 80% from RVT to uHVT
    – Up to 21% from C60 to C90 for HVT
    – Same footprint cell layout for cell fusion for synthesis and P&R
    – Wide operation voltage: 1.2V - 0.9V; Vcc_min= 0.81v
    – Support Turbo mode to boost performance
    – 9T TGO cell library for RTC and always-on circuit

Memory Compiler & I/O IP:

Item Feature Readiness
Memory Compiler HVT SPRAM
V
HVT 1PRF V
HVT VIA ROM V
HVT power gating SPRAM V
HVT power gating 1PRF V
HVT power gating VIA ROM V
uHVT SPRAM (PowerSlash™ with Turbo Mode) V
uHVT 1PRF (PowerSlash™ with Turbo Mode) V
uHVT VIA (PowerSlash™ with Turbo Mode) V
HVT SPRAM (PowerSlash™ with Turbo Mode) V
HVT 1PRF (PowerSlash™ with Turbo Mode) V
HVT VIA ROM (PowerSlash™ with Turbo Mode) V
I/O 5VT IO V
MV IO V
L/H freq. Xtal IO V
RTC IO V
3.3V GPIO V

 

Functional IP:

Item Feature Readiness
Bandgap

Vin : 3.6v ~ 1.0v
Output : 0.75v ± 3%
IQ : 0.3uA
V
LDO Vin : 3.6v ~ 1.0v
Output : 0.9v ± 5%
IQ : 0.8uA
V
LDO Vin : 3.6v ~ 1.3v
Output : 0.9v /1.2v ± 5% (switchable)
IQ : 1uA
V
Voltage detector Vin : 3.6v ~ 3.0v
Low power consumption
V
SAR ADC 12 bit, 1M samples/s
VCC: 3.6 ~ 2.7V
VDD: 1.2 ~ 0.9V
V
R-2R DAC 10 bit, 1MHz, rail to rail output V
RC OSC (HF) Output : 32M/16M/8M/4M/2M Hz
I < 100uA
V
RC OSC (LF) Output : 32KHz
I < 10uA
V
USB 2.0 OTG PHY V

Other 55nm IPs: Click here