Design Planning

The process of this stage is to assess the RTL code by Faraday proprietary design kit ant third-party synthesizing & simulating design tools.

In addition, Faraday provides state-of-art correlated library model for you to implement the verification, and thus enhance the feasibility of your design in a silicon chip.

 

 

 

 

Design Planning
Design Stage Major Task Design Kit/EDA Tool
Design planning
RTL code assessment
Faraday face
Synopsys LEDA
  DFT planning Faraday testplan Insertion
  Logical floorplanning Cadence SoC-Encounter
Synopsys IC Compiler
ATopTech Aprisa
  Netlist/Package checking Faraday fpgc
Faraday mkbnd
  Timing constraint checking Faraday ftcv