Reliability Services

To satisfy customers' qualification need at any level, Faraday provides reliability qualification services to our customers. Our reliability service scope includes:

1. Generic reliability test report

  • Wafer process reliability qualification
    Process reliability qualification report by process similarity
  • Package reliability qualification
    Generic package reliability qualification report by package type similarity
  • Product reliability qualification
    ESD & latch Up test report per specific ASIC project
    Generic qualification report by design & process similarity

2. VAS (Value Added Service) for chargeable reliability testing service
  • Wafer process reliability qualification
    Process reliability test by specific process generation, process condition or ASIC project
  • Package reliability qualification
    Package reliability test by specific ASIC project
  • Product reliability qualification
    Product reliability test by specific ASIC project
    ESD & latch up test by special specification

Faraday is excellent in complete reliability testing service; covering turnkey reliability testing service from lifetime reliability test, environment reliability test, robustness reliability test to system reliability test.

3. Default ESD/Latch-up guaranty

Item Model ASIC Reference
≥90nm <90nm
ESD
HBM ±2KV ±1KV ANSI/ESDA/JEDEC
JS-001-2010
CDM ±500V ±250V JESD22 C101-E
Latch-up ±IT ±100mA ±100mA JESD No.78C
Vovt 1.5*Vmaxsupply 1.5*Vmaxsupply

- The table above is our default guaranty according to JEDEC standard; it does not mean the limitation of our capability in ESD/Latch-up design.
- For special ESD/LU spec., please check the feasibility in project cooking stage with us.
- ESD-MM has been phased out from Faraday’s default qualification items. The special request for ESD-MM should be raised on the project cooking stage.

 

Examples of Reliability Test Service:

  • Early Failure Test (EFT)*
    Early life failure rate (ELFR) measurement is typically performed during product qualifications or as part of ongoing product reliability monitoring activities. These tests measure reliability performance over the product's first several months in the field. It is therefore important to establish a methodology that will accurately project early life failure rate to actual customer use conditions.

  • High Temperature Operating Life (HTOL)
    The HTOL test is performed for the purpose of demonstrating the reliability by accelerating thermally activated failure mechanisms that subject samples to high temperatures under biased operating conditions. FIT (Failure in Time) and MTTF (Mean Time to Failure) can be calculated from HTOL test result.

  • High Temperature Storage Life (HTSL)
    The HTSL test is employed for the purpose of determining the effects of storing devices at elevated temperatures.

  • Highly-Accelerated Stress Test (HAST)
    The HAST is a steady-state temperature-humidity-bias life test. It is performed for the purpose of evaluating the reliability of non-hermetic packaged devices operating in an environment with high humidity. It employs severe conditions of temperature, humidity and bias, which accelerate the penetration of moisture through the external protective materials (encapsulation or seal) or along the interface between the external protective materials and the metallic conductors passing through. When moisture reaches the surface of the die, the applied potential forms an electrolytic cell which corrodes the aluminum, affecting DC parameters through its conduction and eventually causing catastrophic failure by opening the metal.

  • Pressure Cooler Test (PCT)
    The PCT is performed for the purpose of evaluating the moisture resistance of non-hermetic packaged devices. It employs severe conditions of pressure, humidity and temperature not typical of actual operating environments, which accelerate the penetration of moisture through the external protective materials and the metallic conductors passing through them.

  • Temperature Humidity Bias (THB)
    The THB is performed for the purpose of determining the resistance to moisture and corrosion of plastic-encapsulated circuits. The test is less accelerated than the PCT but includes bias on devices.

  • Temperature Cycle Test (TCT)
    The TCT is performed for the purpose of determining the ability of devices to ensure alternate exposures to extremes of high and low temperatures. It accelerates package defects which are sensitive to thermo mechanical stress. Permanent changes in electrical characteristics and physical damage produced during temperature cycle test result principally from mechanical stress caused by thermal expansion and contraction.

  • Temperature Shock Test (TST)
    The TST is performed for the purpose of determining the ability of devices to endure exposure to extreme changes in temperature by thermally stressing the device in suitable fluid(s) at temperature extremes. Permanent changes in electrical characteristics and physical damage produced during thermal shock result principally from mechanical stress caused by thermal expansion and contraction. Thus the test can detect failure mechanisms caused by temperature transients and gradients.

  • Preconditioning Test
    The preconditioning test is performed for the purpose of evaluating the capability of surface mount devices to withstand the stresses imposed by a printed circuit board assembly operation. A properly designed device should survive this preconditioning test with no measurable changes in electrical performance.

  • Electrostatic Discharge (ESD) Test
    The ESD test is performed for the purpose of determining the sensitivity of devices to electrostatic discharge. There are three modes of ESD, which are known as Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM); however, nowadays MM is no longer a recommended qualification item by JEDEC standard.

  • Latch Up Test
    The latch-up test is performed for the purpose of determining the latch-up immunity of CMOS circuits. When latch-up occurs, a large current flows and sustains through power rails (that is, VCC to VSS) until the power is removed. The excessive current flowing through the circuit can cause device failure due to Joule heating.


Faraday's Internal Reliability Qualification Items and Conditions

Test Item
Test Method/Condition
Test Time/
Read Point
Sample Size (ea)
HTOL*
JESD22-A108
125°C/1000hrs/Vccmax
Dynamic BI patterns
1000 hrs
(168,500,1000)
77
HTSL
JESD22-A103
Temp= 150°C
1000 hrs
(168,500,1000)
45
Pre-condition
JEDEC Standard Method A113
TCT(5 cycles)+Bake (24hrs/ 125°C) +
moisture soak (30°C /60%RH/ 192hrs)+
IR reflow(3 times)
---
225
HAST*
JESD22-A110
1.1*Vccmax, Ta= 130°C, 85% R.H., 2.3atm
96 hrs
45
uHAST

JESD22-A108
Ta= 130°C, 85% R.H., 2.3atm

96 hrs
45
TCT
JESD22-A104
High temperature= 150°C /5min
Low temperature= -65°C /5min
500 cycles
45
PCT
JESD22-A102
Ta= 121°C, 100% R.H., 2atm
168 hrs
45
ESD
1. HBM: ANSI/ESDA/JEDEC JS-001-2010
2. **MM: JEDEC Standard JESD22-A115
3. CDM: JEDEC Standard JESD22-C101
---
3/per mode
Latch-up
JEDEC Standard EIA/JESD78
---
3/per mode
* Need extra time/charge for board preparation.
**ESD MM is not Faraday's default qualification item unless the special request is raised by the customer in advance.



Faraday Reliability Conformance Items and Conditions

Test Item
Test Method/Condition
Test Time/
Read Point
Sample Size (ea)
HTOL
125°C /1000hrs/Vccmax
Test is configured to exercise
the maximum number of modes feasible
1000 hrs
(168,500,1000)
77
Pre-condition
JEDEC Standard Method A113
TCT(5 cycles)+Bake (24hrs/ 125°C) +
moisture soak (30°C /60%RH/ 192hrs)+
IR reflow (3 cycles)
---
154
HAST
JEDEC Standard Method A110
Vccmax, Ta= 130°C, 85% R.H.
96 hrs
77
TCT
JESD22-A104
High temperature= 150°C /5min
Low temperature= -65°C /5min
500 cycles
77
Frequency: Quarterly
Selected Product: 0.25µm process and beyond technologies