Add-on Library

The Critical Package for ASIC Success

Faraday UrLib+® is an add-on library package for the third-party library on UMC 40LP process technology. Based on Faraday’s extensive ASIC (application-specific integrated circuit) production experience, UrLib+ features extra sets of cells for optimized PPA (Power/Performance/Area), yield controllability, noise reduction clock cells, robust ESD (electrostatic discharge) protection, and lower ECO (engineering change orders) cost over the traditional physical libraries to enhance SoC (system-on-chip) designs.



No extra cost but additional benefits with UrLib+

  • Seamless integration
  • Lower ECO costs
  • At-speed testability support
  • Robust ESD protection
  • Process variation monitoring
  • Further PPA optimization
    • 4% - 11% chip size reduction
    • ~43% saving in clock tree power through MBFF