White Papers
 
  • CoDesign & CoSimulation for High-speed I/O and Noise Sensitive IPs
      Currently, high-speed IPs are widely used in modern SoC (System On Chip) design. These high-speed IPs, such as DDR3/4, USB2/3, SATA, PCIE, SerDes work in multi-giga bits per second. To make sure these IPs properly work in systems, SI (Signal Integrity) and PI (Power Integrity) issues should be carefully...
       
  • Achieve Fine-grain Leakage Power Optimization Without Additional Manufacturing Cost
      In order to get better leakage reduction results within performance target or to get additional leakage reduction without extra mask and process costs, Faraday introduces the multi-channel-length libraries for UMC 40nm process nodes to help designers achieve their design goals…
       
  • Nano-scale Memory IP Technology
      This paper presents the 40nm/28nm memory IP design challenges and corresponding solutions provided by Faraday withsome silicon-proven results demonstrating the effectiveness. The techniques include the ROM design margin improvement, SRAM read/write-assist scenarios, sensing margin control schemes for the adequate tracking at low VCC, and the cell current boost…
       
  • Mobile Camera and Display with MIPI IP Solutions
      To shorten the time-to-market and increase the reliability and compatibility, MIPI is developed to define the standards of the hardware interfaces and communication protocols for the portable devices. Faraday has developed the complete MIPI CSI-2  and DSI IP solutions to fulfill the demands of the camera and display applications in the portable devices...