Faraday UHS-Lib (Ultra High Speed Library) is designed for high speed application, especially high performance CPU. In the past years, Faraday developed full series of ARM-compliant 32-bit RISC CPU with UHS-Lib and achieve very high operation frequency goal (please refer to the chart below). Faraday library developers also leverage the experience of performance enhancement to create a library with many features dedicated for high speed requirement, such as high-speed flip-flops, pin-swapped cells, and skwed-timing-path cells.
| Performance Advantage |
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| *FA626 is a General-Purpose 32-bit RISC processor (ARM Compliant) with MMU, 32KB I-cache, 32KB D-cache, 8KB internal I-SPAD and 8KB internal D-SPAD. |
Product Features
| Features |
UHS-Lib |
| Common Features |
- Rich set of cell functions for logic optimization
- Abundant driving strengths for timing closure
- Plenty of functional cells with balanced delay for clock tree design
- Corresponding scan and non-scan flip-flops
- All pins are located on routing grids
- Only transistor gates are driven by input pins for all cells
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| Specific Features |
Highly optimized for extreme performance High Speed Cells
- Optimized device P/N width ratio
- High-speed flip-flops
- Pin-swapped cells
- Skewed-timing-path cells
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Product Line up
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UHS-Lib |
| 0.13um |
HS |
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| 90nm |
SP-LVT |
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| SP-RVT |
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| SP-HVT |
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| 65nm |
SP-RVT |
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(press the icon on each item to get the library basic information) |
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