As semiconductor technologies evolve, the possibility of processing highly complicated algorithms within an IC is becoming a reality. This is especially true when it comes to high definition video signal compression/decompression (Codec) over the digital network. One technology stood up above all other codec standards is the H.264. It can be clearly seen that the H.264 is now the industry standard in High-Definition (HD-TV) and Digital Video Broadcasting (DVB) related consumer products.

High definition means tremendous digital data has to be processed and this is why Faraday's H.264 baseline encoder and decoder (FTMCP210 and FTMCP220) put the main emphasis on smart DMA architecture to reduce the DRAM access bandwidth. Additionally, the architecture also provides abundant throughput for the andwidth-hungry peripherals like de-interlace and display controller. To lower the power consumption, a parallel and efficient 6-tap filter is developed in H.264 decoder, FTMCP220, to reach D1, 30fps quality at only 40MHz operating frequency. It also supports resolution up to 1920x1088 at 30fps for high definition applications.

Faraday H.264 encoder, FTMCP210 uses several proprietary techniques like modified full-search algorithm, variable block partition and quarter-pel precision motion vector to achieve almost the same quality as JM. It supports at 720p 30fps (HD) at only 140MHz clock rate and 480p 30fps (SD) at only 52MHz clock rate. De-blocking filter is also implemented to improve the image quality at low bit rate applications.

Faraday's H.264 baseline encoder/decoder technology is built from Faraday'sproprietary Media Creative SoC platform. The complete solution also includes fully verified Ethernet, USB, IDE, SD/MMC controller IP and a proven video data flow. This makes Faraday the right choice in ASIC design service in video phone, surveillance control, and multimedia applications.

Examples of H.264 Applications Developed on Faraday's FIE8100 MediaCreative Platform

FTMCP210 : Faraday H.264 Baseline Video Encoder

The FTMCP210 is a video compression IP core supporting ITU-T Recommendation H.264|ISO/IEC 14496-10 Advance Video Coding Standard (MPEG-4 part 10) baseline profile related applications. The FTMCP210 is a pure hardware engine with a built-in DMA engine to transfer data between system memory and local memory through AMBA® 2.0 AHB bus interface. The FTMCP210 can also be controlled by a host CPU through AMBA® 2.0 AHB interface. By initializing the control registers of the FTMCP210, a frame will be compressed into a bitstream. Thus CPU will service the encoder once per frame. The single-phase clock and standard-cell based approach allows you to quickly integrate the FTMCP210 into your SoC designs.

Benefits

• Almost Good PSNR when compared with JM92 model
• Innovative Modified full-search algorithm for high performance motion estimation
• Several techniques used to optimize DMA controller to reduce DRAM access bandwidth
  • Programmable command chain
  • 2D addressing mode
  • Circular addressing mode
  • Unlimited length burst mode
• Hardware block-base rate-control (CBR/VBR)

System Diagram

Key Features

• Support AHB 2.0 interface
• Compliant with ITU-T Recommendation H.264|ISO/IEC 14496-10 Advance Video Coding Standard (MPEG-4 part 10) baseline profile Level 3.1 standard, with resolutions from 128x96 to 1280x720 @ 30 fps, with a step of 16
• Operation frequencies up to 160 MHz @ 0.18µm process
• Encode D1 30 fps with 1 reference frame @ 50 MHz, 3 reference frames @ 90 MHz
• Pure hardware engine
• Built-in DMA engine to transfer data between system memory and local memory
• Automatic power down mechanism to reduce power consumption
• Motion estimation search range: -24 ~ +24 in horizontal direction, -16 ~ 16 in vertical direction with quarter-pel precision
• Rate control: constant bit rate control and variable bitrate control

Application

• Surveillance & monitoring systems
• Video phone and video conference
• Digital cameras and digital camcorders
• IP cameras
• Mobile phones
• PDAs
• PVRs, STBs
• H.264 recorders/players

FTMCP220 : Faraday H.264 Baseline Video Decoder

The FTMCP220 is a video decompression IP supporting H.264 standard at baseline profile. It is compliant with the ITU-T Recommendation H.264 | ISO/IEC 14496-10 Advanced Video Coding Standard (MPEG-4 Part 10) and capable of decoding video streams at resolutions up to 1920x1088 and at frame rates up to 30 frames per second. The single-phase clock and synthesizable design approach allows customers to quickly integrate the FTMCP220 into their SoC designs.

Benefits

• Supports variable block size motion estimation to enhance quality
• Two-dimension and flexible DMA is developed to reduce the required DRAM bandwidth
• A parallel and efficient 6-tap filter can reduce required operation frequency
• A smart intra-compensation and de-block architectures reduce the size of gate count and memory

System Diagram

Key Features

• Compliant with ITU-T Recommendation H.264 | ISO/IEC 14496-10 Advanced Video Coding Standard (MPEG-4 Part 10)
• Support Baseline Profile and level 1 to 3.0
• Support resolutions up to 1920x1088 @30 fps
• Support Baseline Profile features
  • Variable block size motion estimation
  • Quarter-pixel motion compensation
  • Context-based Adaptive Variable-Length Decoding (CAVLD)
    I and P slices
  • In-loop de-blocking filter
• Does not support Arbitrary Slice Order (ASO) or Flexible Macroblock Ordering (FMO)
• Support AHB 2.0 interface
• Automatic power down mechanism

Applications

• Surveillance and monitoring systems
• Video phone and video conference
• Digital cameras and digital camcoders
• IP cameras
• Mobile phones
• PDAs
• PVRs