Faraday - Partner's IPs

Barco Silex IP (Intellectual Property) design expertise is build up in mainly digital and DSP (Digital Signal Processing) related fields, but with a specialization in image & video and in crypto & security applications.

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IP	Features	Literature
Crypto & security
Multi-purpose AES Crypto Engine BA411E	High-level of scalability: 4, 8 or 20 S-Boxes Support interleaved ECB, CTR, CCM and GCM modes for higher performances Support 128-bit, 192-bit and 256-bit key length Support encryption and decryption Perform key expansion Support a wide selection of programmable ciphering modes: Non-Chaining Modes (SP800-38A):ECB and CTR Chaining Modes (SP800-38A):CBC, CFB and OFB Chaining Modes (SP800-38B):OMAC Encryption + Auth. (SP800-38C):CCM Encryption + Auth. (IEEE 802.1ae):GCM Support "Bypass" or "NULL Cipher" mode for streaming applications Stallable core in FIFO mode Control I/F: APB or AXI4-Lite compliant CPU Data I/F: Slave, FIFO/AXI4-Stream (Streaming) or DMA Off-the-shelf, predictable and silicon-proven solution Counter-measure against SPA and DPA (Simple/Dual power analysis) Self-checking TestBench based on FIPS vectors
DES / 3-DES BA412	64-bit data block encryption and decryption in ECB mode 56-bit key in DES mode, 56 / 112 / 168-bit key in 3DES mode Encryption or decryption performed in 16 cycles for DES, 48 cycles for 3DES 64-bit data input, data output and key input buses 1 clock signal (positive edge), 1 asynchronous reset Compliant with FIPS 800-17 and FIPS 800-20 test specifications
Hash crypto core BA413	Support SHA-1, SHA-256, SHA-384, SHA-512, MD-5... Generic parameters allow customers to get the best trade-off area/capabilities in all configurations 64 or 80 cycles per 512- or 1024-bit chunk depending on the algorithm Data Interface: Support 32- or 64-bit data bus Control Interface: Very simple host interface & handshake mechanism
Universal PK Crypto Engine BA414E	High-level of scalability with solutions implementing 4, 16, 64 or 256 multipliers Highly pipe-lined architecture Support all arithmetic operations in both fields F(p) and F(2m) Modular Addition/Subtraction/Multiplication/Division/Inversion Support arbitrary data and key sizes up to 4096 bits Point Doubling/Addition/Multiplication for ECC-F(p) and F(2m) NIST recommended curves are supported: Prime Field P-192, -224, -256, -384, -521 Binary Field K/B-163, -233, -283, -409, -571 Support a lot of standard Public Key algorithms: Modular Exponentiation, RSA and CRT, Elliptic Curve Cryptography (ECC), Digital Signature Algorithm (DSA) and Elliptic Curve DSA (ECDSA), Primality Test (Rabin-Miller) 100% CPU Offload: Pre-and post-processing automatically executed (no need of external CPU resources) Control Interface: APB-compliant CPU Interface Data interface: Generic Memory Interface controlled by an internal scatter-gather DMA Off-the-shelf and silicon-proven solution Optional add-on for protection against SPA/DPA Deliverables: Netlist or RTL, Scripts for synthesis Self-checking TestBench based on FIPS vectors
Memory controllers
Multi-Port AHB DDR SDRAM Memory Controller BA312	DDR-SDRAM Interface Single Data Rate SDRAM and Double Data Rate SDRAM are supported Compatible to JEDEC standard (JESD79C for DDR). Support Micron, Samsung and Infineon devices, among others DFI 1.0 Compatible Operate at frequencies up to 250 MHz (90nm) Programmable CAS Latency: 2, 2.5 or 3 clock cycles Automatically generates the SDRAM initialization sequence Support up to 14-bit address bus Programmable row and column address bit widths up to: 14-bit row address (max. 16k rows) 11-bit column address (max. 2k columns) 2-bit bank address (max. 4 banks) Configurable Memory Data Bus Support up to 4 chip select signals Programmable burst length Support Auto-Refresh mode, Self-Refresh mode and power-down mode Support all power-saving features (PASR, TCSR & Deep Power Down) for Mobile SDRAM NOP, READ, WRITE, ACTIVE, AUTO REFRESH, PRECHARGE and BURST TERMINATE commands fully supported Auto Precharge option supported The following parameters are programmable: tRAS, tRCD, tRRD, tRP, tWR, tWTR, tXSR, and tRC Support 4 open banks. SDRAM module serial presence detect not supported Able to interface with an EBI (External Bus Interface) AHB Interface Support up to 8 AHB Ports AMBA AHB 2.0 bus-compatible Does not generate SPLIT , RETRY & ERROR responses on the AMBA bus Support all types of AMBA bursts Support AHB data width of 32 (+ narrow access on 16 or 8 bits) Support AHB address width of 32 bits Management of two independent AHB ports
Single-Port AHB SRAM/NOR Flash Controller BA313	Up to 10 chip select lines Individual 8, 16 or 32 bits data bus configuration for each line. Access to separate byte is possible in 16-bit mode, and access to separate byte or half-word in 32-bit mode Individual wait state configuration, from 0 to 31 cycles Little endian architecture Byte lane control Programmable output enable and write enable delays Programmable bus turnaround Write protection Access type configuration : cs, ncs, or ncs & E Non multiplexed and multiplexed data bus 68-type or 80-type interface Wait request signal and optional timeout feature for slow devices Ready signal for NOR flash support APB interface for register configuration External Bus Interface (EBI) support Interrupt signal on timeout event
Single-Port AHB NAND Flash Controller with ECC BA315	Single-Port AMBA AHB 2.0 bus-compatible Support SLC & MLC Nand Flash memory devices Generates Boot Sequence Support handshake signals to interface with an external DMA Controller Error Correction: Reed-Solomon or Hamming All parameters programmable through APB interface Very low power consumption can be obtained by gating clock for ECC Able to interface with an EBI (External Bus Interface) All data transfers are processed through an external buffer memory Best trade-off performance/area by defining generic parameters before synthesis
Single-Port AHB NAND Flash Controller with ECC BA316	Support AMBA 3 AXI protocol (32 or 64-bit Data Width) Support SDR, DDR, DDR2, Mobile SDR & DDR memory devices (8, 16, 32 or 64-bit configurations) Best trade-off performance/area by defining generic parameters before synthesis All parameters programmable through APB Interface Clocking Ratio 1:1, 1:2 or 1:4 between AXI & SDRAM Interfaces Very low power consumption can be obtained by gating several internal clocks Able to interface with an EBI (External Bus Interface) Compliant with DDR PHY Interface Specification (DFI) version 1.0
Ultra-Tiny AHB Multi-Channel DMA Controller BA612	AMBA AHB-lite compliant DMA transfers Support multiple transfer types: memory to memory, peripheral to memory, memory to peripheral Number of DMA channels configurable Support Basic, Auto-request & Ping-Pong Transfer Modes Low gate count solution with channel parameters stored in system memory: Programmable burst length for each channel Programmable transfer width for each channel Programmable transfer type for each channel Programmable transfer mode for each channel Programmable transfer size for each channel Source & Destination addresses All other parameters programmable through APB Interface Fixed priority or round-robin scheme Best trade-off performance/area by defining generic parameters before synthesis
Video
Multi-channel JPEG 2000 decoder BA109	Compliant with JPEG 2000 (ISO/IEC 15444-1) Multi-channel interface Compliant with DCI (Digital Cinema Initiatives) recommendation Integrated Intellectual Property (IP) core for HD and DCI JPEG 2000 Single-FPGA solution for multi-channel: DCI: 2K@24fps, 2K@48fps, 2K3D@24fps, 4K@24fps and 4K3D@24fps HD: 720p30/60, 1080i, 1080p30/60 Custom frame sizes up to 4096x2160 Customizable input bit rate: up to 250Mbps/500Mbps/1Gbps/lossless XYZ, RGB, YUV (4:4:4 or 4:2:2) color spaces with support for ICT/RCT color transform Supported JPEG 2000 parameters: Wavelet filters: 9/7 and 5/3, 0 to 6 decomposition levels Full-frame decoding (no tiling) Pixel depth: up to 12 bits per color sample Fully autonomous decoder with automatic parameter extraction, minimal user intervention
Multi-channel JPEG 2000 encoder IP BA110	Compliant with JPEG 2000 (ISO/IEC 15444-1) Multi-channel interface Compliant with DCI (Digital Cinema Initiatives) recommendation Integrated Intellectual Property (IP) core for HD and DCI JPEG 2000 Single-FPGA solution for multi-channel: DCI: 2K@24fps, 2K@48fps, 2K3D@24fps, 4K@24fps and 4K3D@24fps HD: 720p30/60, 1080i, 1080p30/60 Custom frame sizes up to 4096x2160 Customizable output bit rate: up to 250Mbps/500Mbps/1Gbps/lossless XYZ, RGB, YUV (4:4:4 or 4:2:2) color spaces with support for ICT/RCT color transform Supported JPEG 2000 parameters: Wavelet filters: 9/7 and 5/3, 0 to 6 decomposition levels Full-frame encoding (no tiling) Pixel depth: up to 12 bits per color sample Configurable bit rate on a frame by frame basis with 3 selectable regulation modes Quality: quantization, weights, … Minimal user intervention
Fast JPEG color decoder IP BA115	Compliant with baseline JPEG (ISO/IEC 10918-1) Support for color images (single and multi-scan format) Single clock cycle per pixel component decoding Single clock cycle Huffman decoding Full header parsing capability Automatic on-the-fly Huffman and quantization tables reprogramming from header data Header error catching features Support for full-format and abbreviated-format, including restart markers Simple FIFO interfaces for compressed data and pixel data interfaces Simple CPU interface for decoder programming Easy-to-use status and control interface through six internal registers Programmable external interrupt for event follow-up Four entropy tables (two DC, two AC), four quantization tables Burst image-sequence decoding support for images with identical tables 8x8 block-format pixel output with classical scan order Fully stallable compressed-data interface; stallable pixel interface on a block-by-block basis Fully synchronous hardware design IEEE 1180-1990 compatible IDCT for number precision requirements
Fast JPEG color encoder IP BA116	Compliant with baseline JPEG (ISO/IEC 10918-1) Support for color images (single and multi-scan format) Single clock cycle per pixel component encoding Single clock cycle Huffman encoding Full header building capability Automatic internal Huffman and quantization tables programming based on header data Support for full-format and abbreviated-format, including restart markers and restart interval One-pass encoding scheme with bit rate regulation if enabled Simple FIFO interfaces for compressed data and pixel data interfaces Simple CPU interface for encoder and headers programming Easy-to-use status and control interface Programmable external interrupt for event follow-up Four entropy tables (two DC, two AC), four quantization tables Burst image-sequence encoding support for images with identical tables 8x8 block-format pixel input with classical scan order Fully stallable compressed-data and pixel interfaces
JPEG codec BA119	Half duplex JPEG codec (based on BA115 and BA116 IP cores) High-speed sustained single clock cycle per pixel component encoding and decoding Single clock cycle Huffman decoding and encoding 100% baseline ISO/IEC 10918-1 JPEG compliance for color images (single and multi-scan formats) extending to effective 255-scan support. Full header generation capability with default pre-programmed Huffman and quantization tables or user-definable custom tables in encoding mode. Full header parsing capability and automatic on-the-fly Huffman and quantization tables reprogramming from header data in decoding mode. One-pass encoding scheme with compression ratio regulation. Header error catching features Full baseline JPEG format and abbreviated format support, including restart markers and DNL. Simple FIFO interfaces for compressed data (32 bit) and pixel interface (8 bit) Simple CPU interface for codec control and programming. Easy-to-use status and control interface through 21 internal registers. Programmable external interrupts for event follow-up. For entropy tables (two DC, two AC), four quantization tables. Burst image-sequence encoding support for images with identical tables and color format. Burst image-sequence decoding support for images with identical tables. 8-bit/pixel components. 8x8 block format pixel interface with classical scan order (row by row from left to right). Fully synchronous hardware design. Fully stallable compressed dat-interface, stallable pixel interface on a block-by-block basis. Throughputs ranging from sub CIF 25Hz to SDTV to HDTV1280x720 50Hz
DO-254
Arinc-429 Rx/Tx BA511E	Support ARINC 429 standard part 1, 2 and 3 Developed according to RTCA/DO-254 ED-80 guidance ( DAL-A criteria) Simple synchronous CPU interface Configurable from 1Rx/1Tx up to 32Rx/16Tx ARINC-429 channels Independent channel parameterization via the CPU interface 63 word buffer (FIFO) for each ARINC-429 input channel 31 word buffer (FIFO) for each ARINC-429 output channel FIFO overflow, parity error, frame error Configuration support per channel: Low speed (LS, 12.5kHz) or high speed (HS, 100kHz) mode Enable - Disable