An Affordable Platform-Based Solution for SoC Designs - Structured ASIC

Structured and platform ASICs have established themselves as a solution to fill the gap between FPGAs and standard-cell ASICs. As mask costs escalate and process technology shrinkage translates into multi-million dollar non-recurring engineering costs (NRE) for each ASIC design, a higher minimum volume quantity is required to justify ASIC investments. As an example, Faraday's structured ASIC technology (MPCA) offers approximately 70% of the cell density efficiency and performance, when compared to a standard cell. The lesser efficient power and speed metrics are traded-off for 3x faster turn around time and 1/3 the typical NRE of standard cell ASIC. When compared to FPGAs, a significantly lower unit cost, far superior silicon area usage, lower power consumptions, and faster logic speed can be expected.

A Structured ASIC is divided into two main sections: pre-diffused blocks in standard cell and available metal programmable blocks. For example a 1P 8M profile would have metal layers M1-M2 dedicated to standard cell, while metal layers M3-M7 (M8 for power grid) are available for customer metallization. Faraday's Structured ASICs provide pre-fabricated digital logic structures, memory blocks, uncommitted usable logic gates, DFT structures, scan path, built-in self test (BIST), boundary scan via JTAG, High speed I/Os, and higher level IP building blocks. The logic gates, flip-flops, and higher-level structures can be configured according to desired system functionality.

Example Structured ASIC (Faraday NC-1 )

Profile of 1P7M Structured ASIC

ASIC vs. Faraday Structured ASIC TAT Time

Structured ASIC Value Proposition: Why Should you Use them?

In general there are number of elements that are considered when making a decision to use Structured or Standard cell for the development of an SoC. These decisions revolve around: desired ROI, total NRE budget, relative design complexity and team ASIC design competency, market unit price sensitivity, time to market, absolute power dissipation for the application, and required logic performance.

Increasingly companies are considering using Structured ASICs to develop standard ASSP/SoC products. The following make vs. buy analysis (ASIC/COT vs. use of Structured ASIC) helps bring the value proposition of using a structured ASIC into the perspective, as a platform for designing a standard ASSP. Two competing fabless semiconductor companies embark on the development of a Communcaiton /Storage NIC SoC product with security and TOE functionality. The device requires 16 High-speed SerDes, PCI-Express x8 4 x GbE MACs, 1 x 10GbE MAC, DDR-2 333 MHz, ARM CPU and peripherals. The first fabless company uses a Structured ASIC (in this case Faraday's NC Express product) as the platform for developing its ASSP. The second company decides to pursue an ASIC (or COT) path for its development, knowing that it will benefit from higher margins using this strategy (we have assumed the resulting ASSP will have 27% better margins for this exercise – 50% vs. 77%). Given the direct product fit, the first company takes advantage of a readily available Structured platform that has 50% of the final ASSP design already completed. Additionally, the Structured ASIC platform enables the first company to complete the development with ½ the R&D resources, receive samples much sooner, and only incurs approximately 1/3 the total SoC development expenses of the competing second fables company (including IP purchases, mask set costs and package, assembly, test and qualification). As a result the first company is able to sample approximately two quarters earlier than its competitor (e.g., Q1'08), and consequently able to enter the market earlier with less investment.

Thus, Structured ASICs can offer a very attractive alternative to ASIC or COT development, especially for fabless semiconductor companies that desire more products their product portfolio, need to reduce R&D costs as a percentage of total revenue, value time to market to gain market share, and have limited NRE budgets.

CBU Structured ASIC Products Roadmap

NC Express Platform ASIC vs. ASIC Analysis

Structured ASIC Engagement Model

The MPCA Structured ASIC block is treated in back-end process as hard macro and Faraday uses standard Synopsis and Cadence design tools for Structured ASIC engagements.

Acronyms : F2C: Faraday to provide to customer; C2F: Customer to provide to Faraday Phase1: Spec Evaluation Phase (F2C) Product brief Data sheet Statement of work doc. MPCA integration guide MPCA Library Phase2: EVB Evaluation Phase Chip and EVB EVB user guide Linux 2.4.19 /2.6.14 drivers   Phase3: Chip Implementation Phase Structured ASIC Simulation Environment (F2C) Gate- level netlist/constraints (C2F ) SDF timing report (C2F )