| Analog > Clock |
| > DLL |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
FXDLL011HD0A
|
Input 66M-200M Hz, output 66M-200M Hz, DDR DLL; UMC 90nm SP/RVT Low-K Logic Process. |
Analog_IP |
90nm |
Gold |
|
|
FXDLL062HC0H_R003
|
1.2V 40~90MHz DLL with double frequency multiplier; UMC 0.13um HS/FSG Logic Process
|
Analog_IP |
0.13um |
'13Q4 |
|
|
FXDLL200HR0B
|
1.2V 50-200MHz DLL with programmable phase delay; UMC 0.11um HS/AE (AL Enhancement) Logic Process |
Analog_IP |
0.11um |
'13Q4 |
|
|
FXDLL300HC0H
|
UMC 0.13um HS/FSG Process DLL-based cell that generates four-channel DQS with 13.5% ~ 36.6% timing delay for DDR1 SDRAM controller usage. |
Analog_IP |
0.13um |
Bronze |
|
|
FXDLL310HD0A
|
Input 200-333MHz, output 200-333MHz, DDR2 DLL; UMC 90nm SP/RVT Low-K logic process |
Analog_IP |
90nm |
Bronze |
|
|
FXDLL310HE0A
|
Input 100-400MHz, output 100-400MHz, DDR2 DLL; UMC 65nm SP/RVT LowK Logic Process |
Analog_IP |
65nm |
Bronze |
|
|
FXDLL310HF0A
|
Input 200-400MHz, output 200-400MHz, DDR2 DLL; UMC 55nm SP Low-K Logic Process |
Analog_IP |
55nm |
Silver |
|
|
FXDLL311HA0A
|
Input 100M-200M Hz, output 100M-200M Hz, DDR DLL; 0.18um Logic GII process |
Analog_IP |
0.18um |
Gold |
|
|
FXDLL311HB0G
|
Input 100M-200M Hz, output 100M-200M Hz, DDR DLL; 0.15um SP Logic process |
Analog_IP |
0.15um |
Silver |
|
|
FXDLL311HC0H
|
Input 100M-200M Hz, output 100M-200M Hz, DDR DLL; 0.13um Logic HS (FSG) process |
Analog_IP |
0.13um |
Platinum |
|
|
FXDLL311HP0A
|
Input 100M-200M Hz, output 100M-200M Hz, DDR DLL; UMC 0.162um Logic Process
|
Analog_IP |
0.162um |
Bronze |
|
|
FXDLL340HA0A
|
Input 100M-150M Hz, output 100M-150M Hz, DDR DLL; 0.18um Logic GII process |
Analog_IP |
0.18um |
Gold |
|
|
FXDLL340HD0A
|
Input 333M-667M Hz, output 333M-667M Hz, DDR2/3 Multi-phase DLL; UMC 90nm SP/RVT LowK Logic Process |
Analog_IP |
90nm |
Silver |
|
|
FXDLL340HF0A
|
Input 80-320MHz, output 6.25%~50% delay,80-320MHz, DDR2 DLL; UMC 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
Silver |
|
|
FXDLL341HC0H_R
|
1.2V 50-202.5MHz DLL with programable phase delay; UMC 0.11um HS/FSG Logic Process
|
Analog_IP |
0.13um |
'13Q4 |
|
|
FXDLL341HR0B
|
1.2V 50-202.5MHz DLL with programable phase delay; UMC 0.11um HS/AE (AL Enhancement) Logic Process |
Analog_IP |
0.11um |
'13Q4 |
|
|
FXDLL350HC0H
|
It is a 0.13?m HS DLL-based cell that generates three-channel DQS with 13.5% ~ 36.6% timing delay for DDR2 SDRAM controller usage. |
Analog_IP |
0.13um |
Bronze |
|
|
FXDLL360HD0A
|
Input 18M-45M Hz, output 18M-45M Hz, timing generator DLL; UMC 90nm SP/RVT Lowk process
|
Analog_IP |
90nm |
Bronze |
|
|
FXDLL380HC0H
|
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage ; UMC 0.13um HS/FSG Process |
Analog_IP |
0.13um |
Bronze |
|
|
FXDLL380HR0B
|
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXDLL380HR0H
|
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage ; UMC 0.11um HS/RVT Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
| |
 |
| |
| Analog > Clock |
| > Digitized DLL |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
FXADDLL310HD0A
|
Input 333M-800MHz, output 333M-800MHz, all digital DLL with one-channel DQS delay range ;UMC 90nm SP/RVT LowK Logic Process |
Analog_IP |
90nm |
Bronze |
|
|
FXADDLL310HE0A
|
Input 333M-800MHz, output 333M-800MHz, all digital DLL with one-channel DQS delay range ; UMC 65nm SP/RVT LowK Logic Process
|
Analog_IP |
65nm |
Bronze |
|
|
FXADDLL310HE0L
|
Input 200M-533MHz, output 200M-533MHz, all digital DLL with two-channel DQS delay range ; UMC 65nm LP/RVT LowK Logic Process. |
Analog_IP |
65nm |
Bronze |
|
|
FXADDLL310HF0A
|
Input 333M-800MHz, output 333M-800MHz, all digital DLL with one-channel DQS delay range ; UMC 55nm SP/RVT LowK Logic Process
|
Analog_IP |
55nm |
Bronze |
|
|
FXADDLL310HF0L
|
Input 333M-800MHz, output 333M-800MHz, all digital DLL with one-channel DQS delay range ; UMC 55nm LP/RVT LowK Logic Process
|
Analog_IP |
55nm |
Bronze |
|
|
FXADDLL310HH0L
|
Input 333M-800MHz, output 333M-800MHz, all digital DLL with one-channel DQS delay range ; UMC 40nm LP/RVT LowK Logic Process
|
Analog_IP |
40nm |
Bronze |
|
|
FXADDLL323HE0L
|
Input 333M-800MHz, output 333M-800MHz, all digital DLL with one-channel DQS delay range ; UMC 65nm LP/RVT LowK Logic Process
|
Analog_IP |
65nm |
Bronze |
|
|
FXADDLL340HF0A
|
Input 333M-800MHz, output 333M-800MHz, all digital DLL with per 1/64UI programmable delay ; UMC 55nm SP/RVT Low-K Logic Process |
Analog_IP |
55nm |
Silver |
|
|
FXADDLL340HJ0G
|
Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPM Process
|
Analog_IP |
28nm |
'13Q4 |
|
|
FXADDLL340HR0B
|
Input 52-208MHz, output 52-208MHz, All digital DLL; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
|
Analog_IP |
0.11um |
'13Q4 |
|
|
FXDEL010HR0B
|
Input 20M-100MHz, output 20M-100MHz, all digital delay line; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
| |
 |
| |
| Analog > Clock |
| > Digitized PLL |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
FXADPLL096HR0B
|
Input 10MHz - 120MHz, output 60MHz - 960MHz, all digital PLL with per 1/32UI programmable delay ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXADPLL327HR0B
|
Input 32.768K Hz, output 12MHz, ADPLL; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
'13Q4 |
|
|
| |
 |
| |
| Analog > Clock |
| > Digitized SSCG |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
FXDLSSC011HR0B
|
All Digital Delay-Based Spread Spectrum Clock Generator ; UMC 0.11um HS/ALE (AL-Enhancement) Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXDLSSC011HR0H
|
All Digital Delay-Based Spread Spectrum Clock Generator ; UMC 0.11um HS/FSG Logic Process
|
Analog_IP |
0.11um |
ASIC Silver |
|
|
FXDLSSC012HR0B
|
All Digital Delay-Based Spread Spectrum Clock Generator ; UMC 0.11um HS/ALE (AL-Enhancement) Logic Process ; MR=0.6%~3% @90MHz TT |
Analog_IP |
0.11um |
Bronze |
|
|
FXSSCG601HR0B
|
5GHz SSCG with 25MHz reference clock; UMC 0.11um HS/AE (AL Advanced Enhancement) 1P8M2T Logic Process |
Analog_IP |
0.11um |
'13Q4 |
|
|
FXSSCG601HR0Q
|
5GHz SSCG with 25MHz reference clock; UMC 0.11um HS/AE (AL Advanced Enhancement) 1P8M2T Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXSSCG602HH0L
|
Input clock range:5 ~ 1280 MHz, output clock range:15.625 ~ 2000 MHz wide-range SSCG; UMC UMC 40nm LP/LVT LowK Logic Process |
Analog_IP |
40nm |
'13Q4 |
|
|
FXSSCG602HR0B
|
Input clock range:10 ~ 1280 MHz, output clock range:15.625 ~ 2000 MHz wide-range SSCG; UMC 0.11um HS/AE (AL Advanced Enhancement) 1P8M2T Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
| |
 |
| |
| Analog > Clock |
| > MiniPLL |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
FXPLL060HA0A
|
Input 20M-200M Hz, output 20M-300M Hz, frequency synthesizable PLL; 0.18um Logic GII process |
Analog_IP |
0.18um |
Platinum |
|
|
FXPLL061HA0A
|
Input 10M-200M Hz, output 20M-300M Hz, frequency synthesizable PLL; 0.18um Logic GII process |
Analog_IP |
0.18um |
Platinum |
|
|
FXPLL120HC0H
|
Input 20M-200M Hz, output 500M-1000M Hz, frequency synthesizable PLL; 0.13um Logic HS (FSG) process |
Analog_IP |
0.13um |
Platinum |
|
|
FXPLL120HE0A
|
Input 20M-200M Hz, output 500M-1000M Hz, frequency synthesizable PLL; UMC 65nm Logic SP/RVT process |
Analog_IP |
65nm |
Silver |
|
|
FXPLL122HC0H
|
Input 20M-200M Hz, output 500M-1000M Hz, frequency synthesizable PLL; UMC 0.13um Logic HS process |
Analog_IP |
0.13um |
Silver |
|
|
FXPLL130HC0H
|
The FXPLL130HC0H is a phase locked loop with an operating range of 250M~500MHz; UMC 0.13um Logic HS(FSG) process |
Analog_IP |
0.13um |
Silver |
|
|
FXPLL130HE0A
|
Input 20M-200M Hz, output 250M-500M Hz, frequency synthesizable PLL; UMC 65nm Logic SP/RVT process
|
Analog_IP |
65nm |
Silver |
|
|
FXPLL131HC0H
|
Input 20M-200M Hz, output 250M-500M Hz, frequency synthesizable PLL; UMC 0.13um Logic HS process |
Analog_IP |
0.13um |
Silver |
|
|
FXPLL132HC0H
|
Input 20M-200M Hz, output 250M-500M Hz, frequency synthesizable PLL; UMC 0.13um Logic HS process |
Analog_IP |
0.13um |
Silver |
|
|
| |
 |
| |
| Analog > Clock |
| > Oscillator |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
FXLCOSC012HR0Q
|
Programmable LC-Oscillator and Divider, Output = 12MHz. Input 1.08V-1.32V ; UMC 0.11um HS/AE (AL Advanced Enhancement) 1P7M1T Logic Process |
Analog_IP |
0.11um |
'13Q4 |
|
|
FXOSC010HD0K
|
Internal-RC, trimmable fixed frequency 10MHz. Input 1.08V-1.32V VBG=0.5V; UMC 90nm Logic LL/RVT Low-K process |
Analog_IP |
90nm |
Bronze |
|
|
FXOSC010HP0A
|
Internal-RC, frequency 10MHz. Input 1.62V-1.98V VBG=0.615V Oscillator; UMC 0.162um GII Logic Process
|
Analog_IP |
0.162um |
Bronze |
|
|
FXOSC020HC0H
|
4M~15MHz R-C Oscillator with External R;UMC 0.13um Logic HS (FSG) process. |
Analog_IP |
0.13um |
Silver |
|
|
FXOSC025HE0L
|
Internal-RC, frequency selected 25 MHz/33MHz. Input 1.08V-1.32V VBG=0.4V; UMC 65nm LP/RVT LowK Logic Process |
Analog_IP |
65nm |
Bronze |
|
|
FXOSC030HC0H
|
15M~50MHz R-C Oscillator with External R;UMC 0.13um Logic HS (FSG) process. |
Analog_IP |
0.13um |
Silver |
|
|
FXOSC040HA0A
|
Internal-RC, trimmable frequency 20MHz, VCCA=1.6V~2.0V VBG=0.615V; UMC 0.18um Logic GII process |
Analog_IP |
0.18um |
'13Q4 |
|
|
FXOSC040HC0H
|
Internal-RC, trimmable fixed frequency 40MHz. Input 1.08V-1.5V VBG=0.615V; UMC 0.13um Logic HS (FSG) process |
Analog_IP |
0.13um |
Silver |
|
|
FXOSC045HA0A
|
Internal-RC, frequency 40MHz. Input 1.6V-2.0V VBG=0.615V; UMC 0.18um Logic GII process |
Analog_IP |
0.18um |
Gold |
|
|
FXOSC045HP0A
|
Internal-RC, frequency 40MHz. Input 1.6V-2.0V VBG=0.615V; UMC 0.162um GII Logic Process |
Analog_IP |
0.162um |
Bronze |
|
|
FXOSC050H90A
|
Internal-RC, trimmable frequency 30MHz, VCCA=2.0V~3.0V VBG=1.23V; UMC 0.25um Logic process |
Analog_IP |
0.25um |
Gold |
|
|
FXOSC050HA0A
|
Internal-RC,trimmable frequency selected 25 KHz/33MHz,VCCA=1.2V~1.8V,VBG=0.615; UMC 0.18um Logic GII process |
Analog_IP |
0.18um |
Gold |
|
|
FXOSC050HA0F
|
UMC 0.18um eFlash Process, Internal-RC,trimmable frequency selected 25MHz/33MHz,VCCA=1.2V~1.8V,VBG=0.615 |
Analog_IP |
0.18um |
Silver |
|
|
FXOSC050HC0H
|
Internal-RC, trimmable fixed frequency 40MHz. Input 1.08V-1.32V VBG=0.8V; UMC 0.13um Logic HS process |
Analog_IP |
0.13um |
Bronze |
|
|
FXOSC050HD0A
|
Internal-RC, trimmable fixed frequency 50MHz. Input 0.9V-1.1V VBG=0.6V; UMC 90nm Logic SP/RVT Low-K process |
Analog_IP |
90nm |
Silver |
|
|
FXOSC050HD0K
|
Internal-RC, trimmable fixed frequency 50MHz. Input 1.08V-1.32V VBG=0.5V; UMC 90nm Logic LL/RVT Low-K process |
Analog_IP |
90nm |
'13Q4 |
|
|
FXOSC050HE0A
|
Internal-RC, trimmable fixed frequency 50MHz, Input 0.9V-1.1V, VBG=0.5V; UMC 65nm Logic SP/RVT Low-K process |
Analog_IP |
65nm |
Bronze |
|
|
FXOSC050HR0H
|
Internal-RC, trimmable fixed frequency 50MHz. Input 1.14V-1.26V VBG=0.8V; UMC 0.11um HS/FSG Logic Process
|
Analog_IP |
0.11um |
Bronze |
|
|
FXOSC055HA0A
|
Internal-RC, frequency 50MHz. Input 1.62V-1.98V VBG=0.615V; UMC 0.18um Logic GII process |
Analog_IP |
0.18um |
Silver |
|
|
FXOSC055HP0A
|
Internal-RC, frequency 50MHz. Input 1.62V-1.98V VBG=0.615V ; UMC 0.162um GII Logic process |
Analog_IP |
0.162um |
Bronze |
|
|
FXOSC055HP0U
|
Internal-RC, frequency 50MHz. Input 2.97V-3.63V VBG=0.615V ; UMC 0.162um EHV 3.3V/8.25V/16.5V Process |
Analog_IP |
0.162um |
Bronze |
|
|
FXOSC060H80A
|
27.5MHz trimmable R-C Oscillator;UMC 0.35um logic process. |
Analog_IP |
0.35um |
Silver |
|
|
FXOSC060H90A
|
External-C, frequency 30KHz~300KHz, VCCA=2.0V~3.0V; UMC 0.25um Logic process |
Analog_IP |
0.25um |
Silver |
|
|
FXOSC060HA0A
|
sub-low current 12KHz RC-Oscillator; UMC 0.18um Logic GII process |
Analog_IP |
0.18um |
Silver |
|
|
FXOSC060HC0H
|
Self-contained ring oscillator, frequency 32KHz. VCC12A=1.08V~1.32V; UMC 0.13um Logic HS process. |
Analog_IP |
0.13um |
Gold |
|
|
FXOSC060HD0A
|
12kHz Ring OSC |
Analog_IP |
90nm |
Bronze |
|
|
FXOSC060HE0A
|
Internal-RC, trimmable fixed frequency 12KHz. Input 0.9V-1.1V; UMC 65nm Logic SP/RVT Low-K process |
Analog_IP |
65nm |
Bronze |
|
|
FXOSC060HE0K
|
Internal-RC, trimmable fixed frequency 12KHz. Input 1.08V-1.32V; UMC 65nm Logic LL/RVT Low-K process |
Analog_IP |
65nm |
Bronze |
|
|
FXOSC060HF0A
|
Output frequency 32KHz. Input 0.9V-1.1V; UMC 55nm SP/RVT LowK Logic Process
|
Analog_IP |
55nm |
'13Q4 |
|
|
FXOSC070HC0H
|
Self-contained ring oscillator, frequency 12KHz. VCC12A=1.08V~1.32V; UMC 0.13um Logic HS process. |
Analog_IP |
0.13um |
Silver |
|
|
FXOSC071HA0A
|
Internal-RC, trimmable frequency selected 50MHz/70MHz. Input 1.62V-1.98V VBG=0.615V; UMC 0.18um Logic GII process |
Analog_IP |
0.18um |
Bronze |
|
|
FXOSC071HC0H
|
Internal-RC, trimmable fixed frequency 70MHz. Input 1.08V-1.32V VBG=0.8V; UMC 0.13um Logic HS/FSG process |
Analog_IP |
0.13um |
ASIC Silver |
|
|
FXOSC071HR0B
|
Internal-R, trimmable fixed frequency 70MHz. Input 1.08V-1.32V VBG=0.8V; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
|
Analog_IP |
0.11um |
Bronze |
|
|
FXOSC071HR0H
|
Internal-RC, trimmable fixed frequency 70MHz. Input 1.08V-1.32V VBG=0.8V; UMC 0.11um HS/FSG Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXOSC080HA0A
|
Internal-RC, trimmable frequency 80MHz. Input 1.62V-1.98V, VBG=0.615V; UMC 0.18um Logic GII process |
Analog_IP |
0.18um |
Bronze |
|
|
FXOSC080HC0H
|
Internal-RC, trimmable fixed frequency 80MHz. Input 1.08V-1.32V VBG=0.8V; UMC 0.13um HS/FSG Logic Process |
Analog_IP |
0.13um |
Bronze |
|
|
FXOSC271HR0B
|
Internal-R, trimmable fixed frequency 70MHz. Input 1.08V-1.32V; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXOSC272HR0H
|
Internal-RC, trimmable fixed frequency 70MHz Power Supply: 1.14V-1.26V; UMC 0.11um HS/FSG Logic Process
|
Analog_IP |
0.11um |
Bronze |
|
|
FXOSC280HF0L
|
Internal-RC and Built-in Bandgap, trimmable fixed frequency 80MHz with register control. Input 1.08V-1.32V; UMC 55nm Logic LP/RVT Low-K process |
Analog_IP |
55nm |
Bronze |
|
|
FXOSC372HR0B
|
Internal-RC, trimmable fixed frequency 70MHz & 82.5MHz. Power Supply: 1.14V-1.26V; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXOSC523HR0B
|
Internal-RC, trimmable fixed frequency 133Mhz. Power Supply: 1.08V-1.32V; UMC 0.11um Logic/MixedMode AE Process
|
Analog_IP |
0.11um |
'13Q4 |
|
|
OSC040H90A
|
External-R, frequency 15MHz~50MHz. VCCA=2.0V~3.0V VBG=1.23V |
Analog_IP |
0.25um |
Gold |
|
|
OSC070H80A
|
Sub-low current with external-C, frequency 10KHz, VCCA=2.0V~3.3V, Ivcca<10uA. |
Analog_IP |
0.35um |
Silver |
|
|
OSC7001
|
Oscillator with frequency 2~15Mhz VCC=3.3V |
Analog_IP |
0.5um |
Silver |
|
|
OSC8005
|
External-R, frequency 15MHz~50MHz, VCCA=2.4V~3.9V VBG=1.23V |
Analog_IP |
0.35um |
Gold |
|
|
| |
 |
| |
| Analog > Clock |
| > Others |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
FXS2D101HH0L
|
IP name: FXS2D101HH0L
Area: 300um*300um
|
Analog_IP |
40nm |
Bronze |
|
|
| |
 |
| |
| Analog > Clock |
| > PLL |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
AP100MA
|
Input 20M-24M Hz, output 20M-100M Hz, frequency synthesizable PLL; 0.5um Logic process |
Analog_IP |
0.5um |
Gold |
|
|
FXPLL010HA0L_APGD
|
Input 1M-200M Hz, output 12.5M-200M Hz, frequency synthesizable PLL with power/ground pad; 0.18um Logic LL process |
Analog_IP |
0.18um |
Silver |
|
|
FXPLL010HB0G
|
Input 5M-200M Hz, output 20M-300M Hz, frequency synthesizable PLL; 0.15um SP Logic process |
Analog_IP |
0.15um |
Silver |
|
|
FXPLL010HB0G_APGD
|
Input 5M-200M Hz, output 20M-300M Hz, frequency synthesizable PLL with power/ground pad; 0.15um SP Logic process |
Analog_IP |
0.15um |
Silver |
|
|
FXPLL010HC0G
|
Input 10M-200M Hz, output 25M-400M Hz, frequency synthesizable PLL; 0.13um Logic SP (FSG) process |
Analog_IP |
0.13um |
Silver |
|
|
FXPLL010HC0G_APGD
|
Output frequency 25M~400MHz PLL;0.13um Logic SP (FSG) process |
Analog_IP |
0.13um |
Silver |
|
|
FXPLL010HC0H
|
Input 5M-200M Hz, output 25M-400M Hz, frequency synthesizable PLL; 0.13um Logic HS (FSG) process |
Analog_IP |
0.13um |
Platinum |
|
|
FXPLL010HC0L
|
Input 5M-200M Hz, output 12.5M-200M Hz, frequency synthesizable PLL; 0.13um Logic LL (FSG) process |
Analog_IP |
0.13um |
Gold |
|
|
FXPLL010HC0L_APGD
|
Input 5M-200M Hz, output 12.5M-200M Hz, frequency synthesizable PLL with power/ground pad; UMC 0.13um Logic LL (FSG) process |
Analog_IP |
0.13um |
Silver |
|
|
FXPLL010HC0U
|
Input 5M-100M Hz, output 20M-400M Hz, frequency synthesizable PLL; 0.13um Logic Fusion (FSG) process |
Analog_IP |
0.13um |
Silver |
|
|
FXPLL010HC0U_APGD
|
Input 5M-100M Hz, output 20M-400M Hz, frequency synthesizable PLL with power/ground pad; 0.13um Logic Fusion (FSG) process |
Analog_IP |
0.13um |
Silver |
|
|
FXPLL010HH0L
|
Input 10-50M Hz, output 10-200M Hz, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process
|
Analog_IP |
40nm |
Bronze |
|
|
FXPLL010HH0L_FTC
|
Input 10-50M Hz, output 10-200M Hz, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process(Note:same schematic with FXPLL010HH0L, but Poly Density Errors are waived in layout for 40% area reduced.)
|
Analog_IP |
40nm |
'13Q4 |
|
|
FXPLL010HR0B
|
Input 10MHz~200MHz, output 25MHz~400MHz, frequency synthesizable PLL; UMC 0.11um LOGIC/MIXEDMODE AE Process |
Analog_IP |
0.11um |
'13Q4 |
|
|
FXPLL010HR0G
|
Input 10MHz~200MHz, output 25MHz~400MHz, frequency synthesizable PLL; UMC 0.11um SP/FSG Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXPLL010HR0I
|
Input 5M-200M Hz, output 12.5M-300M Hz, frequency synthesizable PLL; UMC 0.11um CIS process |
Analog_IP |
0.11um (0.13um Shrink) |
Silver |
|
|
FXPLL010HR0I_APGD
|
Input 5M-200M Hz, output 12.5M-300M Hz, frequency synthesizable PLL with power/ground pad; UMC 0.11um CIS process |
Analog_IP |
0.11um (0.13um Shrink) |
Silver |
|
|
FXPLL011HA0L
|
Input 5M-200M Hz, output 12.5M-200M Hz, frequency synthesizable PLL; 0.18um Logic LL process |
Analog_IP |
0.18um |
Silver |
|
|
FXPLL011HH0L
|
Input 10-50M Hz, output 10-200M Hz, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process
|
Analog_IP |
40nm |
'13Q4 |
|
|
FXPLL019HC0H
|
Input 372M ~ 540MHz, output 5M ~ 400MHz, PLL; UMC 0.13um HS/FSG Logic Process
|
Analog_IP |
0.13um |
Bronze |
|
|
FXPLL019HR0B
|
Input 372M ~ 540MHz, output 5M ~ 197MHz, PLL; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
|
Analog_IP |
0.11um |
'13Q4 |
|
|
FXPLL019HR0H
|
Input 372M ~ 540MHz, output 5M ~ 420MHz, PLL; UMC 0.11um HS/FSG Logic Process
|
Analog_IP |
0.11um |
Bronze |
|
|
FXPLL020HA0A
|
Input 4M-200M Hz, output 20M-400M Hz, frequency synthesizable PLL; 0.18um Logic GII process |
Analog_IP |
0.18um |
'13Q4 |
|
|
FXPLL030HE0K
|
Input 1M-5M Hz, output 15M-600M Hz, frequency synthesizable PLL; UMC 65nm LL-RVT Low-K process |
Analog_IP |
65nm |
Bronze |
|
|
FXPLL030HR0B
|
The PLL is design with UMC 0.11um AE process, with input frequency from 8MHz to 100MHz,and output frequency from 60MHz to 480MHz according to the user setting.
UMC 0.11um AE process.
|
Analog_IP |
0.11um |
'13Q4 |
|
|
FXPLL031HA0A_APGD
|
Input 5M-300M Hz, output 20M-300M Hz, frequency synthesizable PLL with power/ground pad; 0.18um Logic GII process |
Analog_IP |
0.18um |
Platinum |
|
|
FXPLL031HA0F_APGD
|
Input 5M-300M Hz, output 20M-300M Hz, frequency synthesizable PLL with power/ground pad; UMC 0.18um eFLASH process
|
Analog_IP |
0.18um |
Silver |
|
|
FXPLL031HA0L
|
UMC 0.18um LL process Input 5M-300M Hz, output 20M-300M Hz, frequency synthesizable PLL |
Analog_IP |
0.18um |
Silver |
|
|
FXPLL031HD0A
|
Input 5M-300M Hz, output 20M-300M Hz, frequency synthesizable PLL ; UMC 90nm SP/RVT Low-K Logic Process |
Analog_IP |
90nm |
Gold |
|
|
FXPLL031HD0K
|
Input 5M-300M Hz, output 20M-300M Hz, frequency synthesizable PLL; UMC 90nm LL-RVT 1P9M process |
Analog_IP |
90nm |
Silver |
|
|
FXPLL031HE0A
|
Input 5M-500M Hz, output 31.25M-500M Hz, frequency synthesizable PLL; UMC 65nm SP-RVT 1P9M process |
Analog_IP |
65nm |
Silver |
|
|
FXPLL031HE0K
|
Input 5M-300M Hz, output 20M-300M Hz, frequency synthesizable PLL; UMC 65nm LL-RVT 1P10M process |
Analog_IP |
65nm |
Silver |
|
|
FXPLL031HP0A
|
Input 5M-300M Hz, output 20M-300M Hz, frequency synthesizable PLL ; UMC 0.162um Logic Process
|
Analog_IP |
0.162um |
Bronze |
|
|
FXPLL032HC0H
|
Input 20M-200M Hz, output 50M-100M Hz, frequency synthesizable PLL; UMC 0.13um Logic HS process |
Analog_IP |
0.13um |
Bronze |
|
|
FXPLL032HD0A
|
Input 10M-200M Hz, output 300M-600M Hz, frequency synthesizable PLL ; UMC 90nm SP/RVT Low-K Logic Process |
Analog_IP |
90nm |
Silver |
|
|
FXPLL032HD0K
|
Input 20M-200M Hz, output 300M-600M Hz, frequency synthesizable PLL ; UMC 90nm Low Leakage (RVT) Low-K Process |
Analog_IP |
90nm |
Silver |
|
|
FXPLL032HE0A
|
Input 10M-200M Hz, output 300M-600M Hz, frequency synthesizable PLL; UMC 65nm Logic SP-RVT 1P9M process |
Analog_IP |
65nm |
Bronze |
|
|
FXPLL032HE0K
|
Input 20M-200M Hz, output 300M-600M Hz, frequency synthesizable PLL; UMC 65nm Logic LL-RVT Low-K 1P10M process |
Analog_IP |
65nm |
Silver |
|
|
FXPLL032HF0A
|
Input 20M-200M Hz, output 300M-600M Hz, frequency synthesizable PLL ; UMC 55nm SP Low-K Logic Process |
Analog_IP |
55nm |
Silver |
|
|
FXPLL050HA0A
|
Input 5M-200M Hz, output 60M-200M Hz, frequency synthesizable PLL; 0.18um Logic GII process |
Analog_IP |
0.18um |
Silver |
|
|
FXPLL060HA0A
|
Input 20M-200M Hz, output 20M-300M Hz, frequency synthesizable PLL; 0.18um Logic GII process |
Analog_IP |
0.18um |
Platinum |
|
|
FXPLL060HA0F
|
Input 20M-200M Hz, output 20M-300M Hz, frequency synthesizable PLL; UMC 0.18um 1P6M eFlash Process |
Analog_IP |
0.18um |
Silver |
|
|
FXPLL060HD0A
|
Input 20M-200M Hz, output 20M-300M Hz, frequency synthesizable PLL; UMC 90nm SP/RVT Low-K Logic Process |
Analog_IP |
90nm |
'13Q4 |
|
|
FXPLL060HD0K
|
Input 20M-200M Hz, output 20M-300M Hz, frequency synthesizable PLL; UMC 90nm LL/RVT Low-K Logic Process
|
Analog_IP |
90nm |
Bronze |
|
|
FXPLL060HF0A
|
Input 20M-200M Hz, output 20M-300M Hz, frequency synthesizable PLL; UMC 55nm SP/RVT Low-K Logic Process
|
Analog_IP |
55nm |
Silver |
|
|
FXPLL061HA0A
|
Input 10M-200M Hz, output 20M-300M Hz, frequency synthesizable PLL; 0.18um Logic GII process |
Analog_IP |
0.18um |
Platinum |
|
|
FXPLL061HA0F
|
UMC 0.18um eFlash Process Input 10M-200M Hz, output 20M-300M Hz, frequency synthesizable PLL |
Analog_IP |
0.18um |
Bronze |
|
|
FXPLL061HD0A
|
Input 10M-200M Hz, output 20M-300M Hz, frequency synthesizable PLL; UMC 90nm SP/RVT Low-K Logic Process |
Analog_IP |
90nm |
'13Q4 |
|
|
FXPLL061HD0K
|
Input 10M-200M Hz, output 20M-300M Hz, frequency synthesizable PLL; UMC 90nm LL/RVT Low-K Logic Process |
Analog_IP |
90nm |
Bronze |
|
|
FXPLL061HF0A
|
Input 10M-200M Hz, output 20M-300M Hz, frequency synthesizable PLL; UMC 55nm SP/RVT Low-K Logic Process |
Analog_IP |
55nm |
'13Q4 |
|
|
FXPLL061HP0A
|
Input 10M-200M Hz, output 20M~300MHz, frequency synthesizable PLL; UMC 0.162um Logic/Mixed-Mode Process
|
Analog_IP |
0.162um |
Bronze |
|
|
FXPLL062HD0A
|
Input 156.25 MHz, output 625 MHz, frequency synthesizable PLL; UMC 90nm SP/RVT LowK Logic Process.
|
Analog_IP |
90nm |
Bronze |
|
|
FXPLL068HR0B_FTC
|
Input 12M Hz, output 96M~180M Hz, 1.08~1.32V frequency synthesizable PLL; UMC 0.11um HS/AE (AL Advance Enhancement) Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXPLL070HA0A
|
Input 20M-200M Hz, output 20M-300M Hz, frequency synthesizable PLL; UMC 0.18um Logic GII proces. |
Analog_IP |
0.18um |
Silver |
|
|
FXPLL071HA0A
|
Input 10M-200M Hz, output 20M-300M Hz, frequency synthesizable PLL; UMC 0.18um GII Logic process |
Analog_IP |
0.18um |
Silver |
|
|
FXPLL080HE0A
|
Input 25-33.33 MHz, output 600 MHz/800 MHz, 400 MHz/533 MHz, 200 MHz/266 MHz frequency synthesizable PLL; UMC 65nm SP/RVT Low-K Logic Process
|
Analog_IP |
65nm |
Bronze |
|
|
FXPLL080HF0A
|
Input 12MHz, output 800 MHz/1000MHz, 533 MHz/666 MHz, 400 MHz/500 MHz, 266 MHz/533 MHz, frequency synthesizable PLL; UMC 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
Silver |
|
|
FXPLL080HF0A_MTD
|
Input 12MHz, output 900 MHz/1200MHz, 600 MHz/800 MHz, 360 MHz/480MHz, 300 MHz/400MHz, frequency synthesizable PLL; UMC 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
'13Q4 |
|
|
FXPLL110HC0H
|
Input 5M-100M Hz, output 62.5M-1000M Hz, frequency synthesizable PLL; 0.13um Logic HS (FSG) process |
Analog_IP |
0.13um |
Platinum |
|
|
FXPLL110HC0H_APGD
|
Input 5M-100M Hz, output 62.5M-1000M Hz, frequency synthesizable PLL with power/ground pad; 0.13um Logic HS (FSG) process |
Analog_IP |
0.13um |
'13Q4 |
|
|
FXPLL110HD0A
|
This Phase-Locked Loop (PLL) based clock multiplier can generate a stable, high-speed clock from a slower external clock signal. 5/9 bit programmable dividers |
Analog_IP |
90nm |
Silver |
|
|
FXPLL110HF0A
|
Input 10M-100M Hz, output 62.5M-1000M Hz, frequency synthesizable PLL; UMC 55nm SP Low-K Logic Process |
Analog_IP |
55nm |
'13Q4 |
|
|
FXPLL110HH0L
|
Input 10M-200M Hz, output 62.5M-1G Hz, frequency synthesizable PLL; UMC 40 nm LP/RVT Low-K Logic Process |
Analog_IP |
40nm |
'13Q4 |
|
|
FXPLL110HJ0G
|
Input 20M-200M Hz, output 62.5M-1G Hz, frequency synthesizable PLL; UMC 28nm Logic and Mixed-Mode HPM Process
|
Analog_IP |
28nm |
'13Q4 |
|
|
FXPLL120HC0H
|
Input 20M-200M Hz, output 500M-1000M Hz, frequency synthesizable PLL; 0.13um Logic HS (FSG) process |
Analog_IP |
0.13um |
Platinum |
|
|
FXPLL120HD0A
|
Input 20M-36M Hz, output 500M-1000M Hz, frequency synthesizable PLL; UMC 90nm Logic SP RVT-LowK Process. |
Analog_IP |
90nm |
Silver |
|
|
FXPLL120HH0L
|
Input 20M-200M Hz, output 500M-1G Hz, frequency synthesizable PLL; UMC 40nm LP/RVT LowK Logic Process |
Analog_IP |
40nm |
Silver |
|
|
FXPLL120HR0B
|
Input 20M-200M Hz, output 500M-1000M Hz, frequency synthesizable PLL; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
|
Analog_IP |
0.11um |
Platinum |
|
|
FXPLL120HR0H
|
Input 20M-200M Hz, output 500M-1000M Hz, frequency synthesizable PLL; UMC 0.11um HS/FSG Logic Process |
Analog_IP |
0.11um |
'13Q4 |
|
|
FXPLL122HC0H
|
Input 20M-200M Hz, output 500M-1000M Hz, frequency synthesizable PLL; UMC 0.13um Logic HS process |
Analog_IP |
0.13um |
Silver |
|
|
FXPLL130HC0H
|
The FXPLL130HC0H is a phase locked loop with an operating range of 250M~500MHz; UMC 0.13um Logic HS(FSG) process |
Analog_IP |
0.13um |
Silver |
|
|
FXPLL130HR0B
|
Input 20M-200M Hz, output 250M-500M Hz, frequency synthesizable PLL; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
Silver |
|
|
FXPLL131HC0H
|
Input 20M-200M Hz, output 250M-500M Hz, frequency synthesizable PLL; UMC 0.13um Logic HS process |
Analog_IP |
0.13um |
Silver |
|
|
FXPLL132HC0H
|
Input 20M-200M Hz, output 250M-500M Hz, frequency synthesizable PLL; UMC 0.13um Logic HS process |
Analog_IP |
0.13um |
Silver |
|
|
FXPLL134HC0H
|
Input 12M-20M Hz, output 250M-500M Hz, frequency synthesizable PLL; UMC 0.13um Logic HS process |
Analog_IP |
0.13um |
Platinum |
|
|
FXPLL134HD0A
|
Input 12M-200M Hz, output 250M-500M Hz, frequency synthesizable PLL; UMC 90nm Logic SP process |
Analog_IP |
90nm |
Gold |
|
|
FXPLL134HE0A
|
miniPLL (TM) Phase-Locked Loop (PLL) with an operating frequency range of between 31.5 MHz and 500 MHz ; UMC 65nm SP/RVT LowK Logic Process |
Analog_IP |
65nm |
Bronze |
|
|
FXPLL134HF0A
|
miniPLL (TM) Phase-Locked Loop (PLL) with an operating frequency range of between 250 MHz and 500 MHz ; UMC 55nm Logic SP-RVT (LowK) Process |
Analog_IP |
55nm |
'13Q4 |
|
|
FXPLL135HD0A
|
Input 25/50MHz, output 400MHz, frequency synthesizable PLL; UMC 90nm SP/RVT Low-K Process
|
Analog_IP |
90nm |
Silver |
|
|
FXPLL150HD0A
|
Input 25M-200M Hz, output 1000M-1500M Hz, frequency synthesizable PLL; UMC 90nm SP/RVT Low-K Logic Process. |
Analog_IP |
90nm |
Gold |
|
|
FXPLL150HD0K
|
Input 20M-40M Hz, output 1000M-1500M Hz, frequency synthesizable PLL; UMC 90nm Low Leakage (RVT) Low-K Process
|
Analog_IP |
90nm |
Bronze |
|
|
FXPLL150HE0A
|
Input 25M-500M Hz, output 1000M-1500M Hz, frequency synthesizable PLL; UMC 65nm SP-RVT 1P9M process |
Analog_IP |
65nm |
Silver |
|
|
FXPLL150HE0K
|
Input 20M-200M Hz, output 1000M-1500M Hz, frequency synthesizable PLL; UMC 65nm LL-RVT Low-K process |
Analog_IP |
65nm |
'13Q4 |
|
|
FXPLL150HF0A
|
Input 33M-300M Hz, output 1000M-1500M Hz, frequency synthesizable PLL; UMC 55nm SP-RVT Low-K process |
Analog_IP |
55nm |
Silver |
|
|
FXPLL160HD0A
|
Input 33MHz/66MHz, output 1056MHz, frequency synthesizable PLL; UMC 90nm SP/RVT Low-K Logic Process. |
Analog_IP |
90nm |
Silver |
|
|
FXPLL163HR0H_APGD
|
Input 16k-32k Hz, output 32M-128M Hz, PLL; UMC 0.11um HS/FSG Logic Process |
Analog_IP |
0.11um |
'13Q4 |
|
|
FXPLL168HC0H
|
Input 20M-200M Hz, output 250M-500M Hz (with duty ratio 40%~60%) and 125M~ 250MHz (with duty ratio 45%~ 55%), frequency synthesizable PLL; UMC 0.13um HS/FSG Logic process |
Analog_IP |
0.13um |
Bronze |
|
|
FXPLL180HC0H
|
High speed clock generator using UMC 0.13um 1.2V HS process. |
Analog_IP |
0.13um |
Silver |
|
|
FXPLL181HC0H
|
UMC 0.13um HS/FSG Process PLL for DDR2. Clock input 25-27MHz, clock output 1050-1070MHz |
Analog_IP |
0.13um |
Gold |
|
|
FXPLL200HF0A
|
Input 10M-125M Hz, output 1000M-2000M Hz, frequency synthesizable PLL; UMC 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
Bronze |
|
|
FXPLL210H80A
|
Input 25M-100M Hz, output 25M-100M Hz, frequency synthesizable PLL; 0.35um Logic process |
Analog_IP |
0.35um |
'13Q4 |
|
|
FXPLL210HR0B
|
A 10MHz fref. input, 1GHz output fractional-N base SSCG
UMC 0.11um ALE Process
|
Analog_IP |
0.11um |
'13Q4 |
|
|
FXPLL220HC0H
|
HS Spread-Spectrum PLL; UMC 0.13um HS/FSG Logic process. |
Analog_IP |
0.13um |
'13Q4 |
|
|
FXPLL220HD0A
|
Input 12M Hz, output 1200M Hz, spread-spectrum PLL; UMC 90nm SP/RVT LowK Logic Process |
Analog_IP |
90nm |
'13Q4 |
|
|
FXPLL225HJ0G
|
Input 25M-50M Hz, output 1000M-2000MHz, frequency synthesizable PLL; UMC 28nm Logic and Mixed-Mode HPM Process
|
Analog_IP |
28nm |
'13Q4 |
|
|
FXPLL230HA0A
|
Input 20M-135M Hz, output 20M-135M Hz SSCG ; UMC 0.18um Logic Process |
Analog_IP |
0.18um |
'13Q4 |
|
|
FXPLL327HD0A
|
Input 32.768K Hz, output 12M-30M Hz, PLL; UMC 90nm Logic SP/RVT Low-k Process |
Analog_IP |
90nm |
Bronze |
|
|
FXPLL327HL0A
|
Input 32.768K Hz, output 12MHz, PLL; UMC 0.153um Logic GII/MM Process
|
Analog_IP |
0.153um |
Silver |
|
|
FXPLL327HR0B
|
Input 32.768KHz, Ouput 12 and 24MHz PLL, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
'13Q4 |
|
|
FXPLL327HR0H
|
Input 32.768K Hz, output 12M-48M Hz, PLL; UMC 0.11um HS/Copper Logic Process. |
Analog_IP |
0.11um |
Bronze |
|
|
FXPLL350HC0H
|
Input 66.66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 0.13um HS/FSG Logic process
|
Analog_IP |
0.13um |
Bronze |
|
|
FXPLL350HD0A
|
Input 66M-100M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 90nm Logic SP process |
Analog_IP |
90nm |
Bronze |
|
|
FXPLL350HF0A
|
Input 33.33M-100M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm SP-RVT Low-K process |
Analog_IP |
55nm |
Silver |
|
|
FXPLL360HD0A
|
Input 25M-50M Hz, output 667M-1300M Hz, frequency synthesizable PLL; UMC 90nm SP/RVT LowK Logic Process |
Analog_IP |
90nm |
Silver |
|
|
FXPLL360HE0L
|
Input 25M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 65nm LP/RVT LowK Logic Process |
Analog_IP |
65nm |
Bronze |
|
|
FXPLL360HF0L
|
Input 25M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm LP/RVT LowK Logic Process
|
Analog_IP |
55nm |
Silver |
|
|
FXPLL360HH0L
|
Input 25M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process |
Analog_IP |
40nm |
Silver |
|
|
FXPLL360HJ0G
|
Input 25-66M Hz, output 400-800M Hz, frequency synthesizable PLL; UMC 28nm HPM Logic Process |
Analog_IP |
28nm |
'13Q4 |
|
|
FXPLL362HC0H
|
Input 133MHz - 266MHz, output clock_1X 133MHz - 266MHz, output clock_2X 266MHz - 533MHz, output clock_4X 533MHz-1066MHz,frequency synthesizable PLL; UMC 0.13um HS/FSG Logic Process |
Analog_IP |
0.13um |
Bronze |
|
|
FXPLL362HD0A
|
Input 200M-400M Hz, output 800M-1600M 400-800MHz and 200-400MHz , frequency synthesizable PLL; UMC 90nm SP/RVT LowK Logic Process |
Analog_IP |
90nm |
Silver |
|
|
FXPLL362HE0L
|
Input 133MHz - 266MHz, output clock_1X 133MHz - 266MHz, output clock_2X 266MHz - 533MHz, output clock_4X 533MHz-1066MHz,frequency synthesizable PLL;UMC 65nm LP/RVT LowK Logic process
|
Analog_IP |
65nm |
Bronze |
|
|
FXPLL362HF0A
|
Input 200M-400M Hz, output 800M-1600M,400-800MHz and 200-400MHz , frequency synthesizable PLL; UMC 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
Bronze |
|
|
FXPLL362HF0L
|
Input 200MHz - 400MHz, output clock_1X 200MHz - 400MHz, output clock_2X 400MHz - 800MHz, output clock_4X 800MHz-1600MHz,frequency synthesizable PLL;UMC 55nm LP/RVT LowK Logic process
|
Analog_IP |
55nm |
'13Q4 |
|
|
FXPLL362HH0L
|
Input 200MHz - 400MHz, output clock_1X 200MHz - 400MHz, output clock_2X 400MHz - 800MHz, output clock_4X 800MHz-1600MHz,frequency synthesizable PLL;UMC 40nm LP/RVT LowK Logic process
|
Analog_IP |
40nm |
Bronze |
|
|
FXPLL362HJ0G
|
Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400MHz - 1600MHz, output,frequency synthesizable PLL;UMC 28nm HPM Logic Process |
Analog_IP |
28nm |
'13Q4 |
|
|
FXPLL363HE0L
|
Input 200MHz - 400MHz, output clock_1X 200MHz - 400MHz, output clock_2X 400MHz - 800MHz, output clock_4X 800MHz-1600MHz,frequency synthesizable PLL;UMC 65nm LP/RVT LowK Logic process
|
Analog_IP |
65nm |
Bronze |
|
|
FXPLL410H80A
|
Input 15K-100K Hz, output 5M-40M Hz, frequency synthesizable PLL; 0.35um Logic process |
Analog_IP |
0.35um |
'13Q4 |
|
|
FXPLL410H90A
|
Input 90K-1M Hz, output 20M-200M Hz, frequency synthesizable PLL; 0.25um Logic process |
Analog_IP |
0.25um |
'13Q4 |
|
|
FXPLL440HR0B
|
The PLL is design with UMC 0.11um AE process, with input frequency from 10MHz to 12.288MHz,and output frequency from 60MHz to 442.368MHz according to the user setting.
UMC 0.11um AE process. |
Analog_IP |
0.11um |
'13Q4 |
|
|
FXPLL831HD0A
|
Input 5M-100M Hz, output 20M-300M Hz, fractional-N frequency synthesizable PLL; UMC 90nm Logic SP/RVT LowK Process |
Analog_IP |
90nm |
Silver |
|
|
FXPLL899HA0M
|
One output, Integrated LC-VCO, Low-jitter Clock Generator; UMC 0.18um Mixed Mode/RF CMOS 1.8/3.3V 1P6M Process |
Analog_IP |
0.18um |
'13Q4 |
|
|
FXPLL901HA0M
|
1.8-2.0GHz Low-Noise LC-VCO test circuit; UMC 0.18um Mixed Mode/RF CMOS 1.8/3.3V 1P6M Process |
Analog_IP |
0.18um |
'13Q4 |
|
|
FXPLLG020HA0A
|
Input 1M-200M Hz, output 25M-380M Hz, frequency synthesizable PLL; 0.18um Logic GII process |
Analog_IP |
0.18um |
'13Q4 |
|
|
FXPLLG020HP0A
|
Input 1MHz - 200MHz, output clock 25MHz - 400MHz, frequency synthesizable PLL; UMC 0.162um GII Logic Process
|
Analog_IP |
0.162um |
Bronze |
|
|
FXPLLG031HD0K
|
Input 5MHz-300MHz, output 50MHz-300M Hz, frequency synthesizable PLL; UMC 90nm LL-RVT 1P9M process |
Analog_IP |
90nm |
Silver |
|
|
FXPLLG031HE0A
|
Input 10M-500MHz, Output 31.25M-500MHz, frequency synthesizer PLL, UMC 65nm SP/RVT Low-K Process |
Analog_IP |
65nm |
Silver |
|
|
FXPLLG031HE0K
|
Input 10M-300M Hz, output 20M-300M Hz, frequency synthesizable PLL; UMC 65nm LL-RVT 1P10M process |
Analog_IP |
65nm |
Bronze |
|
|
FXPLLJ010HA0A
|
Input 5M-200M Hz, output 10M-200M Hz, frequency synthesizable low voltage PLL; 0.18um Logic GII process |
Analog_IP |
0.18um |
Silver |
|
|
FXPLLJ011HC0H
|
Input 15M-110M Hz, output 15M-110M Hz, De-skew PLL with 0.9V~1.32V power supply range; UMC 0.13um Logic HS(FSG) process |
Analog_IP |
0.13um |
Bronze |
|
|
FXSSCG220HR0H
|
5GHz SSCG with 25MHz reference clock ; UMC 0.11um 1P6M20T HS/FSG Logic Process |
Analog_IP |
0.11um |
Silver |
|
|
PLL030HA0A
|
Input 1M-300M Hz, output 20M-300M Hz, frequency synthesizable PLL; 0.18um Logic GII process |
Analog_IP |
0.18um |
'13Q4 |
|
|
PLL031HA0A
|
Input 5M-300M Hz, output 20M-300M Hz, frequency synthesizable PLL; 0.18um Logic GII process |
Analog_IP |
0.18um |
Platinum |
|
|
PLL210HA0A
|
Input 960K-200M Hz, output 20M-320M Hz, frequency synthesizable PLL; 0.18um Logic GII process |
Analog_IP |
0.18um |
'13Q4 |
|
|
PLL7G02
|
Input 10M-50M Hz, output 25M-75M Hz, frequency synthesizable PLL; 0.5um Logic process gate array |
Analog_IP |
0.45um |
Silver |
|
|
PLL7G03
|
Input 10M-50M Hz, output 75M-125M Hz, frequency synthesizable PLL; 0.5um Logic process gate array |
Analog_IP |
0.45um |
'13Q4 |
|
|
PLL8001
|
Input 2.8M-50M Hz, output 2.5M-280M Hz, frequency synthesizable PLL; 0.35um Logic process |
Analog_IP |
0.35um |
Gold |
|
|
PLL8002
|
Input 10M-100M Hz, output 40M-200M Hz, frequency synthesizable PLL; 0.35um Logic process |
Analog_IP |
0.35um |
Platinum |
|
|
PLL8002D
|
Input 10M-100M Hz, output 40M-400M Hz, frequency synthesizable PLL; 0.35um Logic process |
Analog_IP |
0.35um |
Platinum |
|
|
PLL8003
|
Input 2M-50M Hz, output 2.5M-280M Hz, frequency synthesizable PLL; 0.35um Logic process |
Analog_IP |
0.35um |
Gold |
|
|
PLL8005
|
Input 3.5M-50M Hz, output 5M-280M Hz, frequency synthesizable PLL; 0.35um Logic process |
Analog_IP |
0.35um |
Gold |
|
|
PLL8007
|
Input 3M-50M Hz, output 5M-280M Hz, frequency synthesizable PLL; 0.35um Logic process |
Analog_IP |
0.35um |
'13Q4 |
|
|
PLL8011
|
Input 5M-100M Hz, output 20M-200M Hz, frequency synthesizable PLL; 0.35um Logic process |
Analog_IP |
0.35um |
'13Q4 |
|
|
PLL8011P
|
Input 1M-100M Hz, output 20M-200M Hz, frequency synthesizable PLL; 0.35um Logic process |
Analog_IP |
0.35um |
'13Q4 |
|
|
PLL8019
|
Input 5M-100M Hz, output 20M-200M Hz, frequency synthesizable PLL; 0.35um Logic process |
Analog_IP |
0.35um |
'13Q4 |
|
|
PLL9011
|
Input 5M-100M Hz, output 20M-200M Hz, frequency synthesizable PLL; 0.25um Logic process |
Analog_IP |
0.25um |
'13Q4 |
|
|
PLL9011T
|
Input 1M-100M Hz, output 20M-200M Hz, frequency synthesizable PLL; 0.25um Logic process |
Analog_IP |
0.25um |
'13Q4 |
|
|
PLL9019
|
Input 5M-100M Hz, output 20M-300M Hz, frequency synthesizable PLL; 0.25um Logic process |
Analog_IP |
0.25um |
Gold |
|
|
PLL9021
|
Input 960K-200M Hz, output 20M-320M Hz, frequency synthesizable PLL; 0.25um Logic process |
Analog_IP |
0.25um |
Silver |
|
|
PLLA002
|
Input 5M-300M Hz, output 20M-300M Hz, frequency synthesizable PLL; 0.18um Logic GII process |
Analog_IP |
0.18um |
'13Q4 |
|
|
PLLA010
|
Input 25M-300M Hz, output 200M-600M Hz, frequency synthesizable PLL; 0.18um Logic GII process |
Analog_IP |
0.18um |
Silver |
|
|
| |
 |
| |
| Analog > Data Communication |
| > DDRII/III |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
FXDDR1A173HF0A
|
DDR1/MDDR PHY CMD/ADDR BLOCK ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process |
Analog_IP |
55nm |
Bronze |
|
|
FXDDR1D173HF0A
|
DDR1/MDDR PHY Data block ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process |
Analog_IP |
55nm |
Bronze |
|
|
FXDDR2A173HE0A
|
DDR2/MDDR PHY CMD/ADDR BLOCK ; UMC 65nm 1.0V process with 2.5V device SP/RVT Lowk Logic Process |
Analog_IP |
65nm |
Bronze |
|
|
FXDDR2A173HF0A
|
DDR2/MDDR Combo PHY CMD ADDR block ; UMC 55nm SP/RVT Lowk Process with 2.5V device |
Analog_IP |
55nm |
'13Q4 |
|
|
FXDDR2A174HE0A
|
DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage ; UMC 65nm 1.0V with 2.5V Device SP/RVT LowK Logic Process |
Analog_IP |
65nm |
Silver |
|
|
FXDDR2A174HF0A
|
DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage; UMC 55nm 1.0V with 2.5V device SP/RVT LowK Logic Process |
Analog_IP |
55nm |
Silver |
|
|
FXDDR2A200HC0H
|
DDR2/MDDR Combo Command/Address Block ; UMC 0.13um HS/FSG Logic Process |
Analog_IP |
0.13um |
Bronze |
|
|
FXDDR2A200HE0L
|
DDR2/DDR1/MDDR Combo Command/Address Block ; UMC 65nm LP/RVT LowK Logic Process |
Analog_IP |
65nm |
Silver |
|
|
FXDDR2A200HR0B
|
Command/address block of 1:2 DDR2-PHY ; 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXDDR2A200HR0H
|
1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process
|
Analog_IP |
0.11um |
Bronze |
|
|
FXDDR2COMP010HE0A
|
DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process |
Analog_IP |
65nm |
Silver |
|
|
FXDDR2COMP010HE0A
|
DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process |
Analog_IP |
65nm |
Silver |
|
|
FXDDR2COMP010HF0A
|
DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
Silver |
|
|
FXDDR2COMP010HF0A
|
DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
Silver |
|
|
FXDDR2COMP011HC0H
|
DDR2 PHY compensation block for 171 series (non BOAC); UMC 0.13um HS/FSG Logic Process |
Analog_IP |
0.13um |
Bronze |
|
|
FXDDR2COMP012HC0H
|
DDR2-PHY compensation block, BOAC; UMC 0.13um HS/FSG process
|
Analog_IP |
0.13um |
ASIC Silver |
|
FXDDR2COMP013HD0A_FT C
|
DDR2-PHY compensation block, BOAC; UMC 90nm SP/RVT Low-K Logic process |
Analog_IP |
90nm |
Platinum |
|
FXDDR2COMP013HD0A_FT C
|
DDR2-PHY compensation block, BOAC; UMC 90nm SP/RVT Low-K Logic process |
Analog_IP |
90nm |
Platinum |
|
|
FXDDR2D172HR0B
|
DDRII Data Block for Chip Application; UMC 0.11um HS/AE (AL Advance Enhancement) Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXDDR2D173HE0A
|
DDR2/MDDR Combo PHY for Chip load usage ; UMC 65NM SP-RVT with 2.5V device LowK Logic Process |
Analog_IP |
65nm |
Bronze |
|
|
FXDDR2D173HF0A
|
DDR2/MDDR COMBO PHY Data block for Chip usage ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process |
Analog_IP |
55nm |
'13Q4 |
|
|
FXDDR2D174HE0A
|
DDR2/MDDR PHY Data block ; UMC 65nm 1.0V with 2.5V device SP/RVT LowK Logic Process |
Analog_IP |
65nm |
Silver |
|
|
FXDDR2D174HF0A
|
DDR2/MDDR Combo PHY data block ; UMC 55nm SP process with 2.5V device |
Analog_IP |
55nm |
Silver |
|
|
FXDDR2D200HC0H
|
DDR2/MDDR Combo Data Block ; 0.13um Logic HS/FSG Logic Process |
Analog_IP |
0.13um |
Bronze |
|
|
FXDDR2D200HE0L
|
DDR2/DDR1/MDDR Combo Data Block ; UMC 65nm LP/RVT LowK Logic Process |
Analog_IP |
65nm |
Silver |
|
|
FXDDR2D200HR0B
|
Data block of 1:2 DDR2-PHY ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXDDR2D200HR0H
|
1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process
|
Analog_IP |
0.11um |
Bronze |
|
|
FXDDR3A100HD0A
|
DDR2/3 Combo Command /Address Block (with 2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Process |
Analog_IP |
90nm |
Bronze |
|
|
FXDDR3A100HH0L
|
DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device |
Analog_IP |
40nm |
Bronze |
|
|
FXDDR3A102HH0L
|
DDR3/2 COMBO PHY CMD/ADDR BLOCK for 2 layer 8 bits DDR3 PCB ; UMC 40LP/RVT LowK Logic Process with 2.5V device
|
Analog_IP |
40nm |
Bronze |
|
|
FXDDR3A160HF0A
|
UMC 55NM SP-RVT with 2.5V device DDR23 COMBO PHY CMD/ADDR Block for 2 layer PCB board usage |
Analog_IP |
55nm |
'13Q4 |
|
|
FXDDR3A160HH0L
|
DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device for 2 layer PCB board usage |
Analog_IP |
40nm |
'13Q4 |
|
|
FXDDR3A1FC100HH0L
|
UMC 40nm LP-RVT process Flip Chip CMD/ADDR Block for DIMM version
(One part of CMD/ADDR block) |
Analog_IP |
40nm |
'13Q4 |
|
|
FXDDR3A1FC101HH0L
|
UMC 40NM LP RVT with 2.5V IO DDR23 PHY FLIP CHIP CMD/ADDR BLOCK for Chip version (One part of cmd/addr block) |
Analog_IP |
40nm |
'13Q4 |
|
|
FXDDR3A200HF0A
|
DDR2/3 COMBO PHY CMD/ADDR Block for DIMM version ; UMC 55nm SP/RVT and 2.5V device LowK Logic Process |
Analog_IP |
55nm |
Bronze |
|
|
FXDDR3A2FC100HH0L
|
UMC 40nm LP-RVT process Flip Chip CMD/ADDR Block for DIMM version
(One part of CMD/ADDR block) |
Analog_IP |
40nm |
'13Q4 |
|
|
FXDDR3A2FC101HH0L
|
UMC 40NM LP-RVT with 2.5V device process DDR23 COMBO PHY FLIP CHIP CMD/ADDR BLOCK for CHIP version (one part of CMD/ADDR block) |
Analog_IP |
40nm |
'13Q4 |
|
|
FXDDR3A300HE0L
|
DDR3 CMD PHY for DIMM version ; UMC 65nm LP/RVT LowK Logic Process |
Analog_IP |
65nm |
'13Q4 |
|
|
FXDDR3A300HF0A
|
Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
Bronze |
|
|
FXDDR3A300HF0L
|
Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process |
Analog_IP |
55nm |
Bronze |
|
|
FXDDR3COMP100HD0A
|
DDR2/3 COMBO Compensation block (2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Porcess |
Analog_IP |
90nm |
Bronze |
|
|
FXDDR3COMP100HH0L
|
DDR23 COMBO PHY compensation Block ; UMC 40LP/RVT LowK Logic Process with 2.5V device |
Analog_IP |
40nm |
Bronze |
|
|
FXDDR3COMP200HF0A
|
DDR2/3 COMBO PHY compensation block ; UMC 55nm SP/RVT and 2.5V device LowK Logic Process |
Analog_IP |
55nm |
Bronze |
|
|
FXDDR3COMP300HF0A
|
Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
Bronze |
|
|
FXDDR3COMP300HF0A
|
Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
Bronze |
|
|
FXDDR3COMP300HF0L
|
Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process |
Analog_IP |
55nm |
Bronze |
|
|
FXDDR3D100HD0A
|
DDR2/3 PHY Combo PHY data block (1.0v SP & 2.5V device); UMC 90nm SP/RVT LowK Logic Process |
Analog_IP |
90nm |
Bronze |
|
|
FXDDR3D100HH0L
|
DDR23 COMBO PHY Data Block ; UMC 40nm LP/RVT LowK Logic Process with 2.5V device |
Analog_IP |
40nm |
Bronze |
|
|
FXDDR3D102HH0L
|
DDR3/2 COMBO PHY DATA BLOCK for 2 layer 8 bits DDR3 PCB ; UMC 40LP/RVT LowK Logic Process with 2.5V device
|
Analog_IP |
40nm |
Bronze |
|
|
FXDDR3D160HF0A
|
UMC 55NM SP-RVT with 2.5V device process 16BIT DDR23 COMBO DATA PHY for two layer PCB board usage |
Analog_IP |
55nm |
'13Q4 |
|
|
FXDDR3D160HH0L
|
DDR23 COMBO PHY Data Block ; UMC 40nm LP/RVT LowK Logic Process with 2.5V device (16Bit) |
Analog_IP |
40nm |
'13Q4 |
|
|
FXDDR3D200HF0A
|
DDR2/3 COMBO DATA PHY for DIMM version ; UMC 55nm 1.0V SP/RVT with 2.5V IO device LowK Logic Process |
Analog_IP |
55nm |
Bronze |
|
|
FXDDR3D300HE0L
|
DDR3 PHY Datablock for DIMM version ; UMC 65nm LP/RVT LowK Logic Process |
Analog_IP |
65nm |
'13Q4 |
|
|
FXDDR3D300HF0A
|
Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
Bronze |
|
|
FXDDR3D300HF0A
|
Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
Bronze |
|
|
FXDDR3D300HF0L
|
Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process |
Analog_IP |
55nm |
Bronze |
|
|
FXDDR3DFC100HH0L
|
UMC 40nm LP process Flip Chip DDR23 PHY Data Block for DIMM version |
Analog_IP |
40nm |
'13Q4 |
|
|
FXDDR3DFC101HH0L
|
UMC 40NM RVT and 2.5V Device process DDR23 COMBO FLIP CHIP DATA BLOCK for Chip version |
Analog_IP |
40nm |
'13Q4 |
|
|
FXDDR3LTA102HH0L
|
DDR3/DDR3L/LPDDR2 combo PHY ( not support DDR3 leveling function),
command / address block,UMC 40nm LP/RVT LowK Logic Process. |
Analog_IP |
40nm |
'13Q4 |
|
|
FXDDR3LTCOMP100HH0L
|
compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process . |
Analog_IP |
40nm |
Bronze |
|
|
FXDDR3LTD102HH0L
|
DDR3/DDR3L/LPDDR2 combo PHY ( not support DDR3 leveling function),
data block;UMC 40nm LP/RVT LowK Logic Process . |
Analog_IP |
40nm |
'13Q4 |
|
|
FXDDRIIA171HC0H
|
DDR2 PHY Command/Address Block ; UMC 0.13um HS/FSG Logic Process |
Analog_IP |
0.13um |
Platinum |
|
|
FXDDRIIA172HC0H
|
DDR2 PHY Command/Address Block (for Chip Application); UMC 0.13um HS/FSG Logic Process
|
Analog_IP |
0.13um |
ASIC Silver |
|
|
FXDDRIIA173HD0A_FTC
|
DDR2-PHY command/address block for DRAM chip, BOAC ; UMC 90nm SP/RVT Low-K Logic Process |
Analog_IP |
90nm |
Bronze |
|
|
FXDDRIIA174HD0A
|
DDR2-PHY Command/Address block; UMC 90nm SP/RVT Lowk Process |
Analog_IP |
90nm |
Gold |
|
|
FXDDRIID171HC0H
|
DDR2 PHY Data Block ;UMC 0.13um Logic HS/FSG Process
|
Analog_IP |
0.13um |
Gold |
|
|
FXDDRIID172HC0H
|
DDRII Data Block for Chip Application; UMC 0.13um HS/FSG Logic Process
|
Analog_IP |
0.13um |
ASIC Silver |
|
|
FXDDRIID173HD0A_FTC
|
DDR2-PHY data block with BOAC IO; UMC 90nm SP/RVT Lowk Logic Process |
Analog_IP |
90nm |
'13Q4 |
|
|
FXDDRIID174HD0A
|
DDR2-PHY data block; UMC 90nm SP/RVT Lowk Process |
Analog_IP |
90nm |
Gold |
|
|
| |
 |
| |
| Analog > Data Communication |
| > DisplayPort |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
FXDPRX200HF0L
|
Analog Part of 2-Lane Display Port Receiver ; UMC 55nm LP LVT Logic Process |
Analog_IP |
55nm |
'13Q4 |
|
|
| |
 |
| |
| Analog > Data Communication |
| > LVDS |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
FXISP010HR0B_DTD
|
A 3.3V 8-port (40 channels) ISP Transmitter IP, embedded 1.2V PLL circuits with 0.1~1.62Gbps output ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
'13Q4 |
|
|
FXISP010HR0B_NB60
|
1.2V 4-port (8 channels) ISP Transmitter IP, embedded 1.2V PLL circuits with 0.1~1.62Gbps output ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
'13Q4 |
|
|
FXLVDS168HR0H
|
Low power LVDS Receiver IO 50Mbps; UMC 0.11 um Logic HS/FSG (Cu) Process |
Analog_IP |
0.11um |
'13Q4 |
|
|
FXLVDSRX060HH0L
|
LVDS RX,UMC 40nm LP/RVT LowK Logic Process |
Analog_IP |
40nm |
'13Q4 |
|
|
FXLVDSRX080HH0L
|
LVDS RX IO PAD 500 Mbps ,UMC 40nm LP/RVT LowK Logic Process
|
Analog_IP |
40nm |
'13Q4 |
|
|
FXLVRX020HA0A
|
0.18UM RX (PAD); UMC 0.18um GII Process |
Analog_IP |
0.18um |
'13Q4 |
|
|
FXLVRX020HC0H
|
0.13um LVDS RX I/O PAD; UMC 0.13um HS HVT-FSG Process. |
Analog_IP |
0.13um |
'13Q4 |
|
|
FXLVRX020HD0A
|
2.5V LVDS Receiver 8~135MHz; 90nm SP process
|
Analog_IP |
90nm |
Silver |
|
|
FXLVRX020HF0A
|
DLL-based LVDS RX ; 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
'13Q4 |
|
|
FXLVRX030HF0A
|
Low power LVDS Receiver IO 500Mbps; UMC 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
Silver |
|
|
FXLVRX060HC0H
|
DLL-based LVDS RX; VCC=3.3 for 20M~135MHz and VCC=2.5 for 20M~100MHz operation freq.; UMC 0.13um HS FSG Logic Process |
Analog_IP |
0.13um |
Bronze |
|
|
FXLVRX060HD0A
|
Low power LVDS Receiver 700Mbps ; UMC 90nm SP/RVT Lowk Logic Process |
Analog_IP |
90nm |
Silver |
|
|
FXLVRX060HF0A
|
DLL-based LVDS RX ; 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
Silver |
|
|
FXLVRX080HD0A
|
LVDS RX IO ; UMC 90nm SP/RVT LowK Logic Process |
Analog_IP |
90nm |
Bronze |
|
|
FXLVRX082H80A
|
3.3V 85MHz 4:28 LVDS Receiver; UMC 0.35um logic process. |
Analog_IP |
0.35um |
'13Q4 |
|
|
FXLVRX082HA0A
|
UMC 0.18um GII process 2.5V/3.3V 8-Bit LVDS Receiver |
Analog_IP |
0.18um |
'13Q4 |
|
|
FXLVRX082HC0H
|
20M~135MHz DLL-based LVDS RX; UMC 0.13um HS/FSG Process |
Analog_IP |
0.13um |
'13Q4 |
|
|
FXLVRXBS080HH0L
|
The bias block only for FXLVDSRX080HH0L, UMC 40nm LP/RVT LowK Logic Process |
Analog_IP |
40nm |
'13Q4 |
|
|
FXLVTX020H80A
|
LVDS TX Pad; UMC 0.35um LOGIC Process. |
Analog_IP |
0.35um |
'13Q4 |
|
|
FXLVTX020HA0A
|
0.18um TX PAD; UMC 0.18um LOGIC RVT-FSG Process. |
Analog_IP |
0.18um |
'13Q4 |
|
|
FXLVTX020HC0H
|
0.13um LVDS TX I/O PAD; UMC 0.13um HS HVT-FSG Process |
Analog_IP |
0.13um |
Silver |
|
|
FXLVTX020HD0A
|
2.5V LVDS Transmitter 8~135MHz; 90nm SP process |
Analog_IP |
90nm |
Silver |
|
|
FXLVTX020HF0A
|
2.5V LVDS Transmitter 16~178MHz; 55nm SP/RVT LowK Logic Process
|
Analog_IP |
55nm |
Bronze |
|
|
FXLVTX024HD0A
|
2.5V 4 channel LVDS Transmitter 8~135MHz; UMC 90nm SP/RVT LowK Process
|
Analog_IP |
90nm |
Silver |
|
|
FXLVTX030HD0A
|
Single port LVDS Transmitter PAD 1.25Gbps; UMC 90nm SP/RVT low-K process
|
Analog_IP |
90nm |
Gold |
|
|
FXLVTX030HF0A
|
2.5V LVDS Transmitter 700Mbps; UMC 55nm SP LowK Logic Process |
Analog_IP |
55nm |
Silver |
|
|
FXLVTX033HD0A
|
3.3V LVDS Transmitter 700Mbps; 90nm SP/RVT low-L process |
Analog_IP |
90nm |
Bronze |
|
|
FXLVTX081HA0A
|
1.8V/3.3V 85MHz 35:5 LVDS Transmitter; UMC 0.18um GII logic process.
|
Analog_IP |
0.18um |
'13Q4 |
|
|
FXLVTX082HC0H
|
8M~135MHz DLL-based LVDS TX; UMC 0.13um HS/FSG Process
|
Analog_IP |
0.13um |
'13Q4 |
|
|
FXLVTX100HF0A
|
100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.II; UMC 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
Bronze |
|
|
FXLVTX100HH0L
|
100MHz single-ended to differential clock buffer for UMC 40nm LP. |
Analog_IP |
40nm |
'13Q4 |
|
|
FXLVTX169HC0H
|
100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.I; UMC 0.13um HS/FSG LOGIC/MIXEDMODE Enhance Process |
Analog_IP |
0.13um |
'13Q4 |
|
|
FXMLVD022HA0A
|
3.3V 6-bit 5/6pair 2/1port mini-LVDS transmitter; UMC 0.18um GII Logic Process
|
Analog_IP |
0.18um |
'13Q4 |
|
|
FXMPRX010HD0K
|
MIPI Receiver 80~1000MHz; UMC 90nm LL/RVT LowK Logic Process |
Analog_IP |
90nm |
Bronze |
|
|
| |
 |
| |
| Analog > Data Communication |
| > MIPI |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
FXDPHYRX110HH0L
|
MIPI Receiver 80Mbps-1.5Gbps; 40nm LP LowK Logic Process |
Analog_IP |
40nm |
'13Q4 |
|
|
FXDPHYRX210HH0L
|
MIPI Receiver 80Mbps-1.5Gbps,2 Data lane ; 40nm LP LowK Logic Process |
Analog_IP |
40nm |
'13Q4 |
|
|
FXDPHYRX410HH0L
|
MIPI Receiver 80Mbps-1.5Gbps; 40nm LP LowK Logic Process |
Analog_IP |
40nm |
'13Q4 |
|
|
FXDPHYRX410HH0L_A
|
MIPI Receiver 80Mbps-1.5Gbps; 40nm LP LowK Logic Process |
Analog_IP |
40nm |
'13Q4 |
|
|
FXDPHYTX210HH0L
|
MIPI Transmitter 80~1500MHz with 1-clock lane, 2-data lanes; UMC 40nm LP/RVT/LVT Low-K process |
Analog_IP |
40nm |
'13Q4 |
|
|
FXDPHYTX410HH0L
|
MIPI Transmitter 80~1500MHz with 1-clock lane, 4-data lanes; UMC 40nm LP/RVT/LVT Low-K process |
Analog_IP |
40nm |
'13Q4 |
|
|
FXDPHYTX410HH0L_A
|
MIPI PMA Transmitter 80~1500MHz; UMC 40nm LP/RVT/LVT Low-K process |
Analog_IP |
40nm |
'13Q4 |
|
|
FXMPHY010HH0L
|
MIPI MPHY 6Gbps/lane; UMC 40nm LP Low-K process. |
Analog_IP |
40nm |
'13Q4 |
|
|
FXMPRX010HF0A
|
MIPI Receiver 80~1000MHz; UMC 55nm SP/RVT LowK Logic Process
|
Analog_IP |
55nm |
Bronze |
|
|
FXMPRX010HH0L
|
MIPI Receiver 80Mbps-1Gbps; 40nm LP LowK Logic Process |
Analog_IP |
40nm |
Bronze |
|
|
FXMPRX010HH0L_A
|
MIPI Receiver 80Mbps-1Gbps; 40nm LP LowK Logic Process |
Analog_IP |
40nm |
'13Q4 |
|
|
FXMPRX020HF0A
|
MIPI Receiver 80~1000MHz; UMC 55nm SP/RVT LowK Logic Process
Combo for HiSPi & LVDS & SubLVDS |
Analog_IP |
55nm |
'13Q4 |
|
|
FXMPRX020HH0L
|
MIPI Receiver 80Mbps-1Gbps; Combo PHY for MIPI & HiSPi & LVDS & SubLVDS,40nm LP LowK Logic Process |
Analog_IP |
40nm |
Bronze |
|
|
FXMPTX010HF0A
|
MIPI Transmitter 80~1000MHz; UMC 55nm SP/RVT LowK Logic Process
|
Analog_IP |
55nm |
'13Q4 |
|
|
FXMPTX010HH0L
|
MIPI Transmitter 80~1000MHz; UMC 40nm LP/RVT Low-K process |
Analog_IP |
40nm |
'13Q4 |
|
|
| |
 |
| |
| Analog > Data Converter |
| > A/D Converter |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
ADC010H90A
|
10 bit 30MSPS Differential ADC; UMC 0.25um Logic process |
Analog_IP |
0.25um |
Silver |
|
|
ADC030HA0A
|
6 bit 44MSPS Differential ADC; UMC 0.18um Logic/Mixed-Mode Process |
Analog_IP |
0.18um |
Gold |
|
|
FXADC010HD0A
|
1.0V/3.3V 10Bits 10MSPS~50MSPS Pipelined ADC with optional power scaling; UMC 90nm SP LowK Logic Process |
Analog_IP |
90nm |
Bronze |
|
|
FXADC010HH0L
|
1.1V/2.5V 10Bits 80MSPS Pipelined ADC; UMC 40nm LP/RVT Logic Process
|
Analog_IP |
40nm |
'13Q4 |
|
|
FXADC010HL0A
|
1.8V 10bit 80MSPS Pipelined ADC; UMC 0.153um Logic Process |
Analog_IP |
0.153um |
'13Q4 |
|
|
FXADC010HR0B
|
1.2V/3.3V 10Bit 10MSPS-50MSPS Pipelined ADC with optional power scalable; UMC 0.11um HS/AE Logic process |
Analog_IP |
0.11um |
Bronze |
|
|
FXADC020HD0A
|
1.0V/3.3V 10Bits 10MSPS~50MSPS Dual Channel Pipelined ADC with optional power scaling; UMC 90nm SP LowK Logic Process |
Analog_IP |
90nm |
Bronze |
|
|
FXADC020HH0L
|
1.1V/2.5V 10-Bit 80MSPS Dual-Channal Pipelined ADC; UMC 40nm LP/RVT Logic Process |
Analog_IP |
40nm |
'13Q4 |
|
|
FXADC020HL0A
|
1.8V 10bit 80MSPS Dual-Channel Pipelined ADC; UMC 0.153um Logic Process
|
Analog_IP |
0.153um |
'13Q4 |
|
|
FXADC030H90A
|
6 bit 44MSPS Differential ADC; UMC 0.25um Mixed-Mode process |
Analog_IP |
0.25um |
Gold |
|
|
FXADC050HA0A
|
10 bit 80MSPS Differential ADC; UMC 0.18um Logic/Mixed-Mode Process |
Analog_IP |
0.18um |
Silver |
|
|
FXADC060HA0A
|
10 bit 40MSPS Differential ADC; UMC 0.18um Mixed-Mode process |
Analog_IP |
0.18um |
Silver |
|
|
FXADC060HD0K
|
UMC 90nm LL/RVT Low-K Process; 1.2V/Bi-channels 40MHz 10Bits Pipelined ADC |
Analog_IP |
90nm |
'13Q4 |
|
|
FXADC061HA0A
|
10 bit 40MSPS 2-Channel Differential ADC; UMC 0.18um Logic/Mixed-Mode process |
Analog_IP |
0.18um |
Bronze |
|
|
FXADC061HP0A
|
10 bit 40MSPS 2-Channel Differential ADC; UMC 0.162um Mixed-Mode Logic Process
|
Analog_IP |
0.162um |
Bronze |
|
|
FXADC070HR0B
|
A 1.2V 8Bit 160MSPS Pipelined ADC ; UMC 0.11um AE/HS Logic process
|
Analog_IP |
0.11um |
'13Q4 |
|
|
FXADC071HR0B
|
A 1.2V 10Bit 200MSPS Pipelined ADC ; UMC 0.11um AE/HS Logic process |
Analog_IP |
0.11um |
'13Q4 |
|
|
FXADC110HC0H
|
10 bit 200KSPS single-end ADC; UMC 0.13um Logic HS (FSG) process |
Analog_IP |
0.13um |
Bronze |
|
|
FXADC110HC0H_M8B
|
10 bit 200KSPS, 8-to-1 A/D converter, UMC 0.13um HS(FSG) Logic process.
|
Analog_IP |
0.13um |
Silver |
|
|
FXADC110HP0A
|
6 bit 85KSPS 2-to-1 single-end A/D Converter; UMC 0.162um GII Logic Process |
Analog_IP |
0.162um |
Bronze |
|
|
FXADC120H80A
|
10 bit 300KSPS single End ADC; UMC 0.35um Logic process |
Analog_IP |
0.35um |
Silver |
|
|
FXADC120H90A
|
10 bit 400KSPS single-end ADC; UMC 0.25um Logic process |
Analog_IP |
0.25um |
Silver |
|
|
FXADC1402HC0L_FTCM8A
|
10bit 1MSPS SAR ADC with 8-1 mux ; UMC 0.13um LL/FSG Logic Process |
Analog_IP |
0.13um |
Silver |
|
|
FXADC1402HR0B_FTCM8A
|
10bit 1MSPS SAR ADC with 8-to-1 Mux ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
|
Analog_IP |
0.11um |
Silver |
|
|
FXADC1403HR0B_FTCM8A
|
10bit 1MSPS SAR ADC with 8-1 Mux ; UMC 0.11um AL/HS Logic Process |
Analog_IP |
0.11um |
Silver |
|
|
FXADC140HA0A
|
10 bit 1MSPS single-end ADC; UMC 0.18um Logic GII process |
Analog_IP |
0.18um |
Gold |
|
|
FXADC140HA0A_FTCM8A
|
10 bit 1MSPS single-end ADC with 8-to1 Mux, UMC 0.18um GII Logic Process |
Analog_IP |
0.18um |
Bronze |
|
|
FXADC140HC0L
|
UMC 0.13um LL/FSG Process; 1MSample/s 10-bit SAR ADC with rail-to-rail input feature |
Analog_IP |
0.13um |
Silver |
|
|
FXADC140HC0L_FTCM8A
|
FXADC140HC0L with 8-to1 Mux; UMC 0.13um LL/FSG Logic Process |
Analog_IP |
0.13um |
ASIC Silver |
|
|
FXADC1432HD0A_FTCM8B
|
FXADC1432HD0A with 8-to1 Mux; UMC 90um SP/RVT LowK Logic Process
|
Analog_IP |
90nm |
'13Q4 |
|
|
FXADC1432HR0B_FTCM8A
|
12bit 1MSPS SAR ADC with 8-1 Mux ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
|
Analog_IP |
0.11um |
Silver |
|
|
FXADC143HD0A_FTCM8B
|
FXADC143HD0A with 8-to1 Mux for FTC; UMC 90um SP-RVT Low-K Logic Process
|
Analog_IP |
90nm |
Bronze |
|
|
FXADC143HD0K
|
It is a 11-bit 1 MSPS SAR ADC ; UMC 90nm LL/RVT Low-K Process
|
Analog_IP |
90nm |
Silver |
|
|
FXADC143HE0K_FTCM8A
|
1MSPS 10-bit SAR ADC ; UMC 65nm LL-RVT LowK Logic Process |
Analog_IP |
65nm |
Silver |
|
|
FXADC1502HC0L_FTCM8A
|
12bit 1MSPS SAR ADC with 8-1 Mux (All C-type) ; UMC 0.13um LL/RVT FSG Logic Process |
Analog_IP |
0.13um |
'13Q4 |
|
|
FXADC1502HC0L_FTCM8B
|
12 bit 1MSPS single-end A/D Converter with 8-MUX channel; UMC 0.13um LL/FSG Logic Process
|
Analog_IP |
0.13um |
Bronze |
|
|
FXADC1502HR0B_FTCM8A
|
12bit 1MSPS SAR ADC with 8-1 Mux (All C-type) ; UMC 0.11um HS/AE (AL Advanced Enhnacement) Logic Process
|
Analog_IP |
0.11um |
Silver |
|
|
FXADC150HA0A_FTCM8A
|
10 bit 1MSPS single-end A/D Converter ; UMC 0.18um GII Logic Process |
Analog_IP |
0.18um |
Bronze |
|
|
FXADC150HC0L_FTCM8A
|
10 bit 1MSPS single-end A/D Converter with 8-1MUX; UMC 0.13um LL/RVT FSG Logic Process
|
Analog_IP |
0.13um |
Bronze |
|
|
FXADC150HF0A_FTCM8A
|
10bit 1MSPS SAR ADC with 8-1 Mux (all C-type) ; UMC 55nm SP/RVT LowK Logic Process
|
Analog_IP |
55nm |
Silver |
|
|
FXADC150HL0A_FTCM8A
|
10 bit 1MSPS single-end A/D Converter with 8-1 Mux; UMC 0.153um Logic/Mixed-Mode Process |
Analog_IP |
0.153um (85% shrink of 0.18um) |
Bronze |
|
|
FXADC150HR0B_FTCM8A
|
10bit 1MSPS SAR ADC with 8-1 Mux (All C-type); UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
|
Analog_IP |
0.11um |
Silver |
|
|
FXADC1512HR0B_FTCM8A
|
12-bit 4MSPS SAR ADC with 8-1 Mux (All C-type) ; UMC 0.11um HS/AE (AL Advanced Enhnacement) Logic Process |
Analog_IP |
0.11um |
'13Q4 |
|
|
FXADC156HC0L
|
10-bit 2MSPS,differential input fully-cap SAR ADC ; UMC 0.13um LL/FSG Logic Process |
Analog_IP |
0.13um |
Bronze |
|
|
FXADC162HA0A
|
16 bit 96KSPS differential Sigma-Delta ADC; UMC 0.18um Logic GII process |
Analog_IP |
0.18um |
'13Q4 |
|
|
FXADC182H90A
|
18 bit 96KSPS differential Sigma-Delta ADC; UMC 0.25um Logic process |
Analog_IP |
0.25um |
Silver |
|
|
FXADC183HF0A
|
8 bit 70KSPS SAR ADC;UMC 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
'13Q4 |
|
|
FXADC183HH0L
|
8 bit 70KSPS SAR ADC; UMC 40nm LP/HVT LowK Logic Process |
Analog_IP |
40nm |
'13Q4 |
|
|
FXADC220HA0A
|
10 bit 10MSPS Differential ADC; UMC 0.18um Logic GII process |
Analog_IP |
0.18um |
Silver |
|
|
FXADC230HR0B
|
10bits 10MSPS fully differential sychronous SAR ADC ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
'13Q4 |
|
|
FXADC231HR0B
|
10bits 10MSPS fully differential sychronous SAR ADC ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
|
Analog_IP |
0.11um |
'13Q4 |
|
|
FXADC256HR0B
|
10bits 10MSPS fully differential sychronous SAR ADC ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
|
Analog_IP |
0.11um |
'13Q4 |
|
|
FXADC3021HF0A
|
24-Bit Stereo ADC with seperated digital audio interface ; UMC 55nm SP/RVT LowK Logic Process
|
Analog_IP |
55nm |
Bronze |
|
|
FXADC302HF0A
|
24-Bit Audio Stereo ADCs; UMC 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
Silver |
|
|
FXADC560HC0H
|
A dual channel 12Bit 80MSPS Pipelined ADC ; UMC 0.13um HS/FSG Logic Process |
Analog_IP |
0.13um |
Bronze |
|
|
FXADC560HF0A
|
12-Bits 80MSPS Dual-Channel Pipelined ADC; UMC 55nm SP/RVT Low-K Logic Process
|
Analog_IP |
55nm |
Silver |
|
|
FXADC609HF0A
|
Dual channel wide-band Analog-to-Digital Converter (ADC) based on a continuous-time (CT) sigma-delta (Σ-Δ) modulator that achieves 60-dB of dynamic range over a 20 MHz input bandwidth ; UMC 55nm SP LowK Logic Process |
Analog_IP |
55nm |
'13Q4 |
|
|
FXADC743HD0A
|
SAR ADC with 8-to-1 Mux and resistor-type touch panel deriver ; UMC 90nm SP-RVT LowK Process
|
Analog_IP |
90nm |
Bronze |
|
|
| |
 |
| |
| Analog > Data Converter |
| > Amplifier |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
FXSPK508HF0A
|
5V 1W Mono Speaker Amplifier, UMC 55nm SP/RVT LowK Logic Process. |
Analog_IP |
55nm |
'13Q4 |
|
|
| |
 |
| |
| Analog > Data Converter |
| > Audio ADDA |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
FXADDA1601HC0L
|
24-Bit 96kHz Sampled Mono Audio CODEC with Speaker Driver ; UMC 0.13um LL/FSG Logic Process |
Analog_IP |
0.13um |
Bronze |
|
|
FXADDA1601HD0A_FTC
|
18bit MONO Sigma-Delta Audio Codec with speaker driver; UMC 90nm SP/RVT Low-K logic process |
Analog_IP |
90nm |
Silver |
|
|
FXADDA1601HL0A
|
24-Bit 96kHz Sampled Mono Audio CODEC with Speaker Driver ; UMC 0.153um Logic/Mixed-Mode Process
|
Analog_IP |
0.153um |
Silver |
|
|
FXADDA1602HC0H
|
18/24-Bit 96kHz Sampled Mono Audio CODEC; UMC 0.13um HS/FSG Logic Process |
Analog_IP |
0.13um |
Bronze |
|
|
FXADDA1602HL0A
|
24-Bit 96kHz Sampled Mono Audio CODEC with Speaker Driver & Microphone bias; UMC 0.153um Logic/Mixed-Mode Process
|
Analog_IP |
0.153um (85% shrink of 0.18um) |
Silver |
|
|
FXADDA1608HC0L
|
24-Bit 96kHz Sampled Mono Audio CODEC with Class-D Speaker Driver ; UMC 0.13um LL/FSG Logic Process
|
Analog_IP |
0.13um |
Silver |
|
|
FXADDA160HC0H
|
18/24-Bit 96kHz Sampled Mono Audio CODEC; UMC 0.13um HS/FSG Logic Process
|
Analog_IP |
0.13um |
Bronze |
|
|
FXADDA160HC0L
|
18-Bit 96kHz Sampled Mono Audio CODEC with Speaker Driver; UMC 0.13um LL process. |
Analog_IP |
0.13um |
Silver |
|
|
FXADDA160HL0A
|
24-Bit 96kHz Sampled Mono Audio CODEC with Speaker Driver ; UMC 0.153um Logic/Mixed-Mode Process
|
Analog_IP |
0.153um (85% shrink of 0.18um) |
Silver |
|
|
FXADDA161H90A
|
16 bit 96KHz Sigma-Delta audio Codec; UMC 0.25um Logic process |
Analog_IP |
0.25um |
Silver |
|
|
FXADDA1623HA0A
|
16 bits Audio CODEC DA +10 bit SAR AD + 5 bit SAR AD (The enhancement of FXADDA1622HA0A) ; UMC 0.18um Logic GII process |
Analog_IP |
0.18um |
Bronze |
|
|
FXADDA1625HC0H
|
16bit Sigma-Delta Audio Codec; UMC 0.13um HS/FSG Logic process
|
Analog_IP |
0.13um |
Silver |
|
|
FXADDA1625HP0A
|
16 bits Audio CODEC DA + 5 bit SAR AD (The enhancement of FXADDA1623HA0A) ; UMC 0.162um Logic GII process
|
Analog_IP |
0.162um (0.18um Shrink) |
Bronze |
|
|
FXADDA1626HC0H
|
16bit Sigma-Delta Audio Codec; UMC 0.13um HS/FSG Logic process |
Analog_IP |
0.13um |
Silver |
|
|
FXADDA1628HC0H
|
16bit Sigma-Delta Audio Codec; UMC 0.13um HS/FSG Logic Process
|
Analog_IP |
0.13um |
Bronze |
|
|
FXADDA162HA0A
|
16 bit 96KHz Sigma-Delta audio Codec; UMC 0.18um Logic GII process |
Analog_IP |
0.18um |
Silver |
|
|
FXADDA162HA0P
|
16 bit 96KHz Sigma-Delta low power audio Codec; UMC 0.18um Logic GII process. |
Analog_IP |
0.18um |
Gold |
|
|
FXADDA183H90A
|
18 bit 96KHz Sigma-Delta audio Codec; UMC 0.25um Logic process |
Analog_IP |
0.25um |
Silver |
|
|
FXADDA185H90A
|
18 bit 96KHz Sigma-Delta audio Codec; UMC 0.25um Logic process |
Analog_IP |
0.25um |
Silver |
|
|
FXADDA2001HC0H
|
UMC 0.13um Logic HS proces, multibit DAC + 1-bit ADC and digital core cell using 1-V FSC0H_L |
Analog_IP |
0.13um |
Bronze |
|
|
FXADDA200HD0A
|
24bit 96KHz A/D onverter, 24bit 96KHz D/A Converter, Audio Codec ; UMC 90nm Logic SP/RVT 2.5OD3.3 process |
Analog_IP |
90nm |
Silver |
|
|
FXADDA200HD0D_FTC
|
24bit 96KHz A/D onverter, 24bit 96KHz D/A Converter, Audio Codec ; UMC 90nm SP/RVT+HVT 2.5OD3.3 Logic Process
|
Analog_IP |
90nm |
Bronze |
|
|
FXADDA300HD0A
|
24bit 96KHz Audio Codec ; UMC 90nm Logic SP/RVT 2.5OD3.3 LowK Process |
Analog_IP |
90nm |
Silver |
|
|
FXADDA300HD0A_FTC
|
24bit 96KHz Audio Codec with power switch inside ; UMC 90nm SP/RVT 2.5OD3.3 Logic Process |
Analog_IP |
90nm |
'13Q4 |
|
|
FXADDA300HH0L
|
UMC 40nm high performance stereo audio codec with highly integrated analog functionality system |
Analog_IP |
40nm |
Bronze |
|
|
FXADDA301HR0B
|
24-Bit 96kHz Sampled Mono ADC and Stereo DAC Audio CODEC with Headphone Driver ; UMC 0.11um HS/ALE Logic Process
|
Analog_IP |
0.11um |
Silver |
|
|
FXADDA301HR0H
|
24-Bit 96kHz Sampled Mono ADC and Stereo DAC Audio CODEC with Headphone Driver ; UMC 0.11um HS Logic Process
|
Analog_IP |
0.11um |
Silver |
|
|
FXADDA302HD0A
|
24bit 96KHz Audio Codec ; UMC 90nm SP/RVT 2.5OD3.3V LowK Logic Process
|
Analog_IP |
90nm |
Bronze |
|
|
FXADDA302HH0L
|
24bit 96KHz Audio Codec ; UMC 40nm Logic LP/HVT 2.5OD3.3 process |
Analog_IP |
40nm |
'13Q4 |
|
|
FXADDA302HR0B
|
24-Bit 96kHz Sampled Mono ADC and Stereo DAC Audio CODEC with Headphone Driver ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
|
Analog_IP |
0.11um |
Bronze |
|
|
FXADDA303HR0B
|
24-Bit 96kHz Sampled Mono ADC and Stereo DAC Audio CODEC with Headphone Driver ; UMC 0.11um HS/AE Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXADDA820HA0A
|
2-channel 4MHz 6-bit ADC & 8 bit DAC;UMC 0.18um logic GII process. |
Analog_IP |
0.18um |
Silver |
|
|
| |
 |
| |
| Analog > Data Converter |
| > Communication ADDA |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
FXADDA820H90A
|
6 bit 44MHz dual channel ADC/8-bit 44MHz dual channel DAC; UMC 0.25um Logic process |
Analog_IP |
0.25um |
Gold |
|
|
FXDAC030HD0A
|
10-BIT 100 MHZ 3-CHANNEL DAC; UMC 90nm SP/RVT Low-K Process |
Analog_IP |
90nm |
Gold |
|
|
| |
 |
| |
| Analog > Data Converter |
| > D/A Converter |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
DAC100SHA0A
|
10 bit 150MSPS current output single-end DAC; UMC 0.18um Logic GII process |
Analog_IP |
0.18um |
Gold |
|
|
DAC210HA0A
|
6/8 bit 44MSPS dual channel voltage output differential-end DAC; UMC 0.18um Logic/Mixed-mode Process |
Analog_IP |
0.18um |
Silver |
|
|
DAC7001
|
8 bit 50MSPS voltage output single-end DAC; UMC 0.5um Logic process |
Analog_IP |
0.5um |
Gold |
|
|
FXDAC010HE0K
|
3-channel digital-to-analog converter (DAC) with 10-bit resolution for video application. UMC 65nm 1.2V/2.5V 1P10M low-leakage (LL) process. It is a current-steering type DAC and provides a superior maximum update rate of 75 MHz and this IP only require at least 7 metal layers.
|
Analog_IP |
65nm |
Silver |
|
|
FXDAC020HC0H
|
10 bit 150MSPS current output differential-end DAC; UMC 0.13um Logic HS (FSG) process |
Analog_IP |
0.13um |
Platinum |
|
|
FXDAC020HC0L
|
10 bit 150MSPS current output differential-end DAC; UMC 0.13um Logic LL (FSG) process |
Analog_IP |
0.13um |
Platinum |
|
|
FXDAC020HD0A
|
10 bit 150MSPS current output differential-end DAC; UMC 90nm Logic SP-RVT Low-K process |
Analog_IP |
90nm |
Gold |
|
|
FXDAC020HH0L
|
10bit 150MSPS 1-ch Video DAC,UMC 40nm LP/RVT Low-K process |
Analog_IP |
40nm |
Bronze |
|
|
FXDAC020HL0A
|
10 bit 150MSPS current output differential-end DAC; UMC 0.153um Mixed-Mode/Logic Process
|
Analog_IP |
0.153um |
Silver |
|
|
FXDAC020HR0B
|
10bit 250MSPS current output differential-end D/A Converter ; UMC 0.11um HS/AE (AL Enhance) Logic Process
|
Analog_IP |
0.11um |
Bronze |
|
|
FXDAC021HF0A
|
10bit 150MSPS current output differential-end D/A Converter ; UMC 55nm SP/RVT LowK Logic Process
|
Analog_IP |
55nm |
Bronze |
|
|
FXDAC021HH0L
|
10bit 150MSPS 1-ch Video DAC,UMC 40nm LP/HVT Low-K process |
Analog_IP |
40nm |
Bronze |
|
|
FXDAC022HF0A
|
10bit 150MSPS current output differential-end D/A Converter ; UMC 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
Bronze |
|
|
FXDAC030HA0A
|
10 bit 150MSPS 3 channel current output single-end DAC; UMC 0.18um Logic GII process |
Analog_IP |
0.18um |
Platinum |
|
|
FXDAC030HC0H
|
10 bit 250MSPS 3 channel current output single-end DAC; UMC 0.13um Logic HS (FSG) process |
Analog_IP |
0.13um |
Platinum |
|
|
FXDAC030HD0J
|
10 bit 165MSPS current steering 3-ch DAC; UMC 90nm Logic LL(HVT) Low-K process. |
Analog_IP |
90nm |
Silver |
|
|
FXDAC030HH0L
|
10bit 250MSPS 3-ch Video DAC,UMC 40nm LP/RVT Low-K process |
Analog_IP |
40nm |
Bronze |
|
|
FXDAC030HR0B
|
10bit 250MSPS 3-channle Current-steering Video D/A Converter ; UMC 0.11um HS/AE (AL Enhance) Logic Process
|
Analog_IP |
0.11um |
Bronze |
|
|
FXDAC030HR0H
|
10bit 250MSPS Current-steering Video D/A Converter; UMC 0.11um HS/FSG Logic Process |
Analog_IP |
0.11um |
'13Q4 |
|
|
FXDAC031HF0A
|
A small area 10bit 150MSPS 3-channel Video DAC ; UMC 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
Silver |
|
|
FXDAC032HF0A
|
A small area 10bit 150MSPS 3-channel Video DAC ; UMC 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
Bronze |
|
|
FXDAC033HD0A
|
10 bit 150MSPS 3-channel current output DAC; UMC 90nm SP/RVT LowK Logic Process |
Analog_IP |
90nm |
Bronze |
|
|
FXDAC038HF0A
|
8bit 250MSPS 3-channle Current-steering Video D/A Converter ; UMC 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
Bronze |
|
|
FXDAC038HR0B
|
8bit 250MSPS 3-channle Current-steering Video D/A Converter ; UMC 0.11um HS/AE (AL Advance Enhancement) Logic Process
|
Analog_IP |
0.11um |
Silver |
|
|
FXDAC060HA0A
|
10 bit 44MSPS dual channel differential current output DAC; UMC 0.18um Logic GII process |
Analog_IP |
0.18um |
Silver |
|
|
FXDAC060HC0H
|
10bit 80MSPS current output dual channel D/A Converter, UMC 0.13um 1P8M Logic High Speed process |
Analog_IP |
0.13um |
Silver |
|
|
FXDAC060HP0A
|
10bit 44MSPS current output dual channel D/A Converter, UMC 0.162um Mixed-Mode Logic Process |
Analog_IP |
0.162um |
Bronze |
|
|
FXDAC061HD0K
|
UMC 90nm LL/RVT Low-K Process 10-Bit 80MHz 2-CHANNEL DAC |
Analog_IP |
90nm |
Silver |
|
|
FXDAC103HA0A
|
10-bit DAC for communication system;UMC 0.18um logic GII process. |
Analog_IP |
0.18um |
Silver |
|
|
FXDAC110HA0A
|
10-BITS 1MHZ R-2R DAC; UMC 0.18um GII logic process. |
Analog_IP |
0.18um |
Bronze |
|
|
FXDAC110HC0H
|
10-BITS 1MHZ R-2R DAC; UMC logic 0.13um HS (FSG) process. |
Analog_IP |
0.13um |
Gold |
|
|
FXDAC110HL0A
|
10bit 1MHz Voltage Output R-2R D/A Converter; UMC 0.153um Logic/Mixed-Mode Process |
Analog_IP |
0.153um (85% shrink of 0.18um) |
'13Q4 |
|
|
FXDAC120HF0A
|
10bits 1MHz Voltage output R-2R D/A Converter; UMC 55nm SP-RVT process |
Analog_IP |
55nm |
Bronze |
|
|
FXDAC120HL0A
|
10bit 1MHz Voltage Output R-2R D/A Converter; UMC 0.153um Logic Process |
Analog_IP |
0.153um |
Bronze |
|
|
FXDAC120HR0H
|
10bits 1MHz Voltage output R-2R D/A Converter; UMC 0.11um process
|
Analog_IP |
0.11um |
Bronze |
|
|
FXDAC130HF0A
|
10bits 1MHz R-2R D/A Converter with rail to rail voltage output ; UMC 55nm SP-RVT process
|
Analog_IP |
55nm |
Bronze |
|
|
FXDAC160HD0A
|
18bit MONO Sigma-Delta DAC Codec with speaker driver; UMC 90nm SP/RVT Low-K logic process
|
Analog_IP |
90nm |
Silver |
|
|
FXDAC161H90A
|
16 bit 96KSPS voltage output stereo-line DAC; UMC 0.25um Logic process |
Analog_IP |
0.25um |
Silver |
|
|
FXDAC162H90A
|
16 bit 96KSPS voltage output stereo-line DAC; UMC 0.25um Logic process |
Analog_IP |
0.25um |
Silver |
|
|
FXDAC162HA0A
|
16 bit 96KSPS voltage output stereo-line DAC; UMC 0.18um Logic GII process |
Analog_IP |
0.18um |
Silver |
|
|
FXDAC162HC0L
|
16/18/20/24 bit input format supporting 192KSPS output stereo-line DAC with headphone driver; UMC 0.13um Logic LL (FSG) process |
Analog_IP |
0.13um |
Gold |
|
|
FXDAC260HC0H
|
12-bit 80MHz 2 channel DAC; UMC 0.13um HS/FSG Logic Process |
Analog_IP |
0.13um |
Bronze |
|
|
FXDAC260HF0A
|
80MHz 2-chanel DAC ; UMC 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
Silver |
|
|
FXDAC300HF0A
|
24bit 96KHz Audio Codec ; UMC 55nm SP/RVT 2.5OD3.3 Logic Process |
Analog_IP |
55nm |
Silver |
|
|
FXDAC300HR0B
|
18-Bit 48kHz Sampled Stereo Audio DAC with Headphone Driver ; UMC 0.11 um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
Silver |
|
|
FXDAC3011HR0B
|
24-Bit 96kHz Sampled Stereo Audio DAC with Headphone Driver ; UMC 0.11um HS/AE 1P6M1T Logic Process with MMC+HR |
Analog_IP |
0.11um |
'13Q4 |
|
|
FXDAC302HR0B
|
18-Bit 48kHz Sampled Stereo Audio DAC with Headphone Driver ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
Silver |
|
|
FXDAC302HR0H
|
18-Bit 48kHz Sampled Stereo Audio DAC with Headphone Driver ; UMC 0.11um HS/FSG Logic Process
|
Analog_IP |
0.11um |
Bronze |
|
|
FXDAC500HR0B
|
24-Bit 96kHz Sampled Stereo DAC Audio CODEC with Headphone Driver and Mono 5V Speaker Amplifier; UMC 0.11um HS/ALE Logic Process
|
Analog_IP |
0.11um |
Bronze |
|
|
FXDAC508HR0B
|
24-Bit 96kHz Sampled Stereo DAC Audio CODEC with Headphone Driver and Mono 5V Speaker Amplifier; UMC 0.11um HS/ALE Logic Process
|
Analog_IP |
0.11um |
Bronze |
|
|
| |
 |
| |
| Analog > Others |
| > SSD |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
FXSSD010HA0A
|
UMC 0.18um GII process 20MHz-70MHz delay-type spread-spectrum clock generator. |
Analog_IP |
0.18um |
Silver |
|
|
| |
 |
| |
| Analog > Power |
| > Band Gap |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
BG020HA0L
|
VBG=0.615V, VCCA=1.8V, VCCA_min=1.0V, Ivcca=23uA; UMC 0.18um Logic GII process low voltage. |
Analog_IP |
0.18um |
Silver |
|
|
BGA001
|
VBG=1.23V, VCCAH=3.3V, VCCAH_min=2.0V, Ivccah=25uA; UMC 0.18um Logic GII process. |
Analog_IP |
0.18um |
Silver |
|
|
FXBG010H80A
|
The FXBG010H80A is a complete bandgap voltage reference circuit with low temperature coefficient, and high power supply rejection ratio with output voltage VBG=1.23 V. UMC 0.35um Logic Process. |
Analog_IP |
0.35um |
Gold |
|
|
FXBG010H90A
|
VBG=1.23V, VCCAH=3.3V, VCCAH_min=2.0V, Ivccah=25uA; UMC 0.25um Logic process. |
Analog_IP |
0.25um |
Silver |
|
|
FXBG010HC0A
|
VBG=1.23V, VCCAH=3.3V, VCCAH_min=2.0V, Ivccah=23uA; UMC 0.13um Logic HS (FSG) process. |
Analog_IP |
0.13um |
Gold |
|
|
FXBG010HD0A
|
Input 2.25V-2.75V, VBG=1.23V, Bnad Gap, SP process; UMC 90nm SP/RVT (FSG) Logic process |
Analog_IP |
90nm |
Bronze |
|
|
FXBG010HE0A
|
Input 2.25V-2.75V, VBG=1.23V, Band Gap, SP process; UMC 65nm SP/RVT Low-K Logic process
|
Analog_IP |
65nm |
Bronze |
|
|
FXBG010HE0K
|
Input 2.25V-2.75V, VBG=1.23V, Band Gap, LL process; UMC 65nm LL/RVT LowK Logic process |
Analog_IP |
65nm |
Bronze |
|
|
FXBG010HE0L
|
Input 2V-3.6V, VBG=1.2V,Band Gap;UMC 65nm LP/RVT LowK Logic Process UHS library
|
Analog_IP |
65nm |
Bronze |
|
|
FXBG010HF0A
|
Input 2.25V-2.75V, VBG=1.23V, Band Gap, SP process; UMC 55nm SP/RVT LowK Logic process |
Analog_IP |
55nm |
Bronze |
|
|
FXBG010HH0L
|
Input 2V-3.6V, VBG=1.23V BandGap; UMC 40nm LP/RVT LowK Logic Process |
Analog_IP |
40nm |
Bronze |
|
|
FXBG010HL0A
|
Input 2.0V-3.6V, VBG=1.22V, Band Gap ; UMC 0.153um 1.8V/3.3V Logic/Mixed-Mode Process |
Analog_IP |
0.153um |
Bronze |
|
|
FXBG010HR0B
|
Input 2V-3.6V, VBG=1.207V BandGap ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXBG011HH0L
|
Input 2.5V, VBG=1.23V BandGap; UMC 40nm LP/RVT LowK Logic Process
|
Analog_IP |
40nm |
'13Q4 |
|
|
FXBG020H80U
|
Input 3V-3.6V, VBG=1.23V BandGap; UMC 0.35um CDMOS Process |
Analog_IP |
0.35um |
Bronze |
|
|
FXBG020H90A
|
VBG=1.23V, VCCA=2.5V, VCCA_min=1.5V, Ivcca=22uA; UMC 0.25um Logic process. |
Analog_IP |
0.25um |
Gold |
|
|
FXBG020HA0A
|
VBG=0.615V, VCCA=1.8V, VCCA_min=1.0V, Ivcca=30uA; UMC 0.18um Logic GII process. |
Analog_IP |
0.18um |
Gold |
|
|
FXBG020HA0L
|
VBG=0.615V, VCCA=1.8V, VCCA_min=1.0V, Ivcca=23uA; UMC 0.18um Logic LL process. |
Analog_IP |
0.18um |
Silver |
|
|
FXBG020HB0A
|
VBG=0.615V, VCCA=1.5V, VCCA_min=1.0V, Ivcca=23uA; UMC 0.15um SP Logic process. |
Analog_IP |
0.15um |
Silver |
|
|
FXBG020HC0H
|
VBG=0.8V, VCCA=1.2V, VCCA_min=1.0V, Ivcca=47uA, HS process; UMC 0.13um Logic HS (FSG) process. |
Analog_IP |
0.13um |
'13Q4 |
|
|
FXBG020HC0L
|
VBG=0.8V, VCCA=1.2V, VCCA_min=1.0V, Ivcca=45uA; UMC 0.13um Logic LL (FSG) process. |
Analog_IP |
0.13um |
Silver |
|
|
FXBG020HD0A
|
Input 0.9V-1.1V, VBG=0.5V, Band Gap ; UMC 90nm Logic SP-RVT Low-K Process |
Analog_IP |
90nm |
Bronze |
|
|
FXBG020HE0K
|
Input 1.2V, VBG=0.8V BandGap; UMC 65nm LL/RVT LowK Logic Process
|
Analog_IP |
65nm |
'13Q4 |
|
|
FXBG020HF0L
|
Input 1.2V, VBG04=0.4V BandGap; UMC 55nm LP/RVT Low-K Logic Process |
Analog_IP |
55nm |
Bronze |
|
|
FXBG020HH0L
|
Input 1.1V, VBG=0.8V, Band Gap,UMC 40nm LP/RVT LowK Logic Process |
Analog_IP |
40nm |
'13Q4 |
|
|
FXBG020HL0A
|
Input 1.2V-1.98V, VBG=0.615V BandGap ; UMC 0.153um Logic Process |
Analog_IP |
0.153um |
Bronze |
|
|
FXBG020HR0B
|
Input 1V-1.5V, VBG=0.8V BandGap ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXBG020HR0H
|
Input 1V-1.5V, VBG=0.8V BandGap ; UMC 0.11um HS/FSG Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXBG021HA0A
|
UMC 0.18um process 1.8V power supply bandgap reference circuit (layout data base with trimming pad) , VBG=0.615V |
Analog_IP |
0.18um |
Gold |
|
|
FXBG021HD0K
|
Input 1.08V-1.32V, VBG=0.6V, Band Gap, LL process; UMC 90 nm Logic LL-RVT Low-K process |
Analog_IP |
90nm |
Bronze |
|
|
FXBG030HA0A
|
VBG=0.615V, VCCAH=3.3V, VCCAH_min=1.2V, Ivccah=25uA; UMC 0.18um Logic GII process. |
Analog_IP |
0.18um |
Silver |
|
|
FXBG030HA0L
|
0.18um,LL,Bandgap,VBG=0.615 at VCCAH=1.2V~4V; UMC 0.18um Logic LL process. |
Analog_IP |
0.18um |
Silver |
|
|
FXBG030HC0H
|
Input 1.0V-1.5V, VBG=0.615V, Bnad Gap, HS process; UMC 0.13um Logic HS (FSG) process |
Analog_IP |
0.13um |
Silver |
|
|
FXBG030HP0U
|
Input 1.8V-3.6V, VBG=0.615V, Band Gap ; UMC 0.162um HV-DDD Process |
Analog_IP |
0.162um |
Bronze |
|
|
FXBG030HR0B
|
Input 1V-1.5V, VBG=0.615V BandGap ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXBG110HA0A
|
Input power range = 2.0V-4.0V, VBG=1.23V, Bandgap, UMC 0.18um Logic GII process |
Analog_IP |
0.18um |
Silver |
|
|
| |
 |
| |
| Analog > Power |
| > Linear Regulator |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
FXPWM070HL0A
|
5.0V to 3.3V high efficiency converter with 300mA driving capability PWM Regulator ; UMC 0.153um 1.8V/3.3V Logic/Mixed-Mode Process |
Analog_IP |
0.153um |
Silver |
|
|
FXREG010HA0A
|
3.3V with 70mA driving capability, Istb=66uA Linear Regulator; 0.18um Logic GII process |
Analog_IP |
0.18um |
'13Q4 |
|
|
FXREG010HC0A
|
3.3V with 50mA driving capability, Istb=70uA Linear Regulator; 0.13um Logic HS (FSG) process |
Analog_IP |
0.13um |
Silver |
|
|
FXREG010HE0A
|
3.3V to 2.5V with 150mA driving capability; Linear Regulator; UMC 65nm SP/RVT LowK Logic Process |
Analog_IP |
65nm |
Bronze |
|
|
FXREG010HE0K
|
3.3V to 2.5V with 200mA driving capability; Linear Regulator; UMC 65nm LL/RVT LowK Logic Process |
Analog_IP |
65nm |
Bronze |
|
|
FXREG010HH0L
|
3.3V to 2.5V with 50mA driving capability; Linear Regulator; UMC 40nm LP/RVT LowK Logic Process |
Analog_IP |
40nm |
Bronze |
|
|
FXREG010HL0A
|
3.3V to 1.8V with 120mA driving capability, VBG=0.615V, Linear Regulator; UMC 0.153um Logic Process |
Analog_IP |
0.153um |
Bronze |
|
|
FXREG010HR0H
|
3.3V to 1.8V with 100mA driving capability; Linear Regulator; UMC 0.11um HS/FSG Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXREG011HC0L_FTC
|
1.8V to 1.2V with 30mA driving capability, Istb=75uA Linear Regulator; UMC 0.13um LL/FSG Logic Process
|
Analog_IP |
0.13um |
Bronze |
|
|
FXREG011HD0K
|
1.8V to 1.2V with 60mA driving capability, Istb=80uA; Linear Regulator; UMC 90nm Logic LL-RVT(LowK) process.
|
Analog_IP |
90nm |
Bronze |
|
|
FXREG011HE0A
|
1.8V to 1.0V with 60mA driving capability; Linear Regulator; UMC 65nm SP/RVT LowK Logic Process
|
Analog_IP |
65nm |
'13Q4 |
|
|
FXREG011HF0A
|
3.3V to 2.8V with 20mA driving capability; Linear Regulator; UMC 55nm SP/RVT Logic Process |
Analog_IP |
55nm |
Bronze |
|
|
FXREG011HH0L
|
3.3V to 2.5V with 100mA driving capability; Linear Regulator; UMC 40nm LP/RVT LowK Logic Process |
Analog_IP |
40nm |
Bronze |
|
|
FXREG012HD0K
|
1.4V~3.6V to 1.2V with 100mA driving capability; Linear Regulator; UMC 90nm LL/RVT LowK LOGIC PROCESS minLib Cell Library |
Analog_IP |
90nm |
'13Q4 |
|
|
FXREG012HF0A
|
3.3V to 2.8V with 20mA driving capability; Linear Regulator; UMC 55nm SP/RVT Logic Process
|
Analog_IP |
55nm |
Silver |
|
|
FXREG012HR0B
|
3.3V to 2.8V with 20mA driving capability; Linear Regulator; UMC 0.11 um AE/HS Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXREG020HA0A
|
3.3V with 150mA driving capability, Istb=96uA Linear Regulator; 0.18um Logic GII process |
Analog_IP |
0.18um |
Platinum |
|
|
FXREG020HA0F
|
3.3V to 1.8V LDO regulator with 150mA driving.Iq=66uA, UMC 0.18um eFlash process |
Analog_IP |
0.18um |
Silver |
|
|
FXREG020HB0A
|
3.3V with 100mA driving capability, Istb=65uA Linear Regulator; 0.15um SP Logic process |
Analog_IP |
0.15um |
'13Q4 |
|
|
FXREG020HC0A
|
3.3V with 100mA driving capability, Istb=65uA Linear Regulator; 0.13um Logic HS (FSG) process |
Analog_IP |
0.13um |
Silver |
|
|
FXREG020HD0A
|
2.5V to 1.2V with 100mA driving capability, Istb=50uA; Linear Regulator; UMC 90nm SP/RVT Low-K Process |
Analog_IP |
90nm |
Bronze |
|
|
FXREG020HE0K
|
3.3V to 1.2V with 150mA driving capability, Istb=200uA; Linear Regulator; UMC 65nm LL/RVT LowK Logic Process |
Analog_IP |
65nm |
Bronze |
|
|
FXREG020HE0L
|
3.3V to 1.2V with 150mA driving capability, Istb=200uA; Linear Regulator; UMC 65nm LP/RVT LowK Logic Process |
Analog_IP |
65nm |
'13Q4 |
|
|
FXREG020HF0A
|
3.3V to 1.0V with 150mA driving capability; Linear Regulator; UMC 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
Bronze |
|
|
FXREG020HF0L
|
3.3V to 1.2V with 150mA driving capability; Linear Regulator; UMC 55nm LP/RVT LowK Logic Process |
Analog_IP |
55nm |
Bronze |
|
|
FXREG020HH0L
|
3.3V to 1.1V with 150mA driving capability; Linear Regulator; UMC 40nm LP/RVT LowK Logic Process |
Analog_IP |
40nm |
Bronze |
|
|
FXREG020HL0A
|
3.3V to 1.8V LDO regulator with 150mA driving.Iq=66uA, UMC 0.153um Mixed-Mode/Logic Process |
Analog_IP |
0.153um (85% shrink of 0.18um) |
Silver |
|
|
FXREG020HP0A
|
3.3V to 1.8V LDO regulator with 150mA driving.Iq=66uA ; UMC 0.162um Logic Process
|
Analog_IP |
0.162um |
Bronze |
|
|
FXREG020HR0B
|
3.3V to 1.2V with 150mA driving capability; Linear Regulator; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXREG021HR0H
|
3.3V to 2.5V with 300mA driving capability; Linear Regulator; UMC 0.11um Logic HS/FSG Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXREG022HR0B
|
3.3V to 1.2V with 400mA driving capability; Linear Regulator; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXREG023HC0H
|
UMC 0.13um Logic HS (FSG) process 3.3V to 1.2V with 100mA driving capability; High PSRR linear Regulator
|
Analog_IP |
0.13um |
Bronze |
|
|
FXREG024HC0H
|
UMC 0.13um Logic HS (FSG) process 3.3V to 1.2V with 100mA driving capability, Linear Regulator with Capacitor-Free |
Analog_IP |
0.13um |
Gold |
|
|
FXREG024HR0H
|
3.3V to 1.2V with 120mA driving capability; Linear Regulator; UMC 0.11um HS/FSG Logic Process
|
Analog_IP |
0.11um |
Bronze |
|
|
FXREG028HR0B
|
3.3V to 1.2V with 150mA driving capability; Non-trim Linear Regulator; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
Silver |
|
|
FXREG030H90A
|
3.3V with 250mA driving capability, Istb=85uA Linear Regulator; 0.25um Logic process |
Analog_IP |
0.25um |
Gold |
|
|
FXREG030HA0A
|
3.3V with 60mA driving capability, Istb=85uA Linear Regulator; 0.18um Logic GII process |
Analog_IP |
0.18um |
Gold |
|
|
FXREG030HC0H
|
3.3V to 1.2V, 1.0V and 0.8V with 50mA driving capability for each, Istb=130uA; Linear Regulator. UMC 0.13um Logic HS (FSG) process |
Analog_IP |
0.13um |
Silver |
|
|
FXREG041HA0A
|
3.3V with 240mA driving capability, Istb=uA Linear Regulator; 0.18um Logic GII process |
Analog_IP |
0.18um |
Platinum |
|
|
FXREG041HA0L
|
3.3V with 240mA driving capability, Istb=uA Linear Regulator; 0.18um Logic LL process |
Analog_IP |
0.18um |
Silver |
|
|
FXREG050H80F
|
5V with 150mA driving capability, Istb=120uA Linear Regulator; 0.35um Logic process |
Analog_IP |
0.35um |
'13Q4 |
|
|
FXREG060H80A
|
5V with 250mA driving capability, Istb=120uA Linear Regulator; 0.35um Logic process |
Analog_IP |
0.35um |
Bronze |
|
|
FXREG060HA0A
|
5V with 250mA driving capability, Istb=120uA Linear Regulator; 0.18um Logic GII process |
Analog_IP |
0.18um |
Platinum |
|
|
FXREG060HA0F
|
5V to 3.3V and 1.8V with 250mA and 70mA driving capability, Istb=200uA; Linear Regulator; UMC 0.18um eFlash process
|
Analog_IP |
0.18um |
Silver |
|
|
FXREG060HC0H
|
5V to 3.3V(200mA) & 1.2V(110mA) audio solution regulator;UMC 0.13um Logic HS (FSG) process |
Analog_IP |
0.13um |
'13Q4 |
|
|
FXREG060HR0H
|
Input 4.5V-5.5V; 3.3V/150mA Output Regulator; UMC 0.11um HS/FSG Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXREG061HA0A
|
5V to 3.3V/1.8V with 250mA/70 mA driving capability, Istb=80uA; Linear Regulator; UMC 0.18um GII process. |
Analog_IP |
0.18um |
Silver |
|
|
FXREG061HR0B
|
Input 4.5V-5.5V; 3.3V/350mA and 1.2V/100mA Voltage Regulator; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXREG062HR0H
|
Input 4.5V-5.5V; 3.3V/350mA and 1.2V/350mA Voltage Regulator;UMC 0.11um HS/FSG Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXREG070HL0A
|
5.0V to 4.2V Linear Regulator with 1000mA driving capability ; UMC 0.153um 1.8V/3.3V Logic/Mixed-Mode Process |
Analog_IP |
0.153um |
Bronze |
|
|
FXREG070HR0B
|
5V to 3.3V with 300mA driving capability; Cascode Structure Regulator;
UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXREG100HH0L
|
3.3V to 1.1V with 150mA driving capability; High accuracy Non-trim Linear Regulator; UMC 40nm LP/RVT LowK Logic Process |
Analog_IP |
40nm |
Bronze |
|
|
FXREG140H80A
|
5V with 50mA driving capability, Istb=124uA Linear Regulator; 0.35um Logic process |
Analog_IP |
0.35um |
Gold |
|
|
FXREG200HH0L
|
3.3V to 1.1V with 100mA driving capability; Fast Transient Linear Regulator; UMC 40nm LP/RVT LowK Logic Process |
Analog_IP |
40nm |
'13Q4 |
|
|
FXREG210HA0A
|
(Preliminary) 3.3V with 120mA driving capability, Istb=60uA Linear Regulator; 0.18um Logic GII process |
Analog_IP |
0.18um |
Silver |
|
|
FXREGSATA168HD0A
|
2 port Linear regulator for FXSATA168HD0A ; UMC 90nm SP/RVT LowK Logic Process |
Analog_IP |
90nm |
Bronze |
|
|
REG7001
|
5V with 110mA driving capability, Istb=120uA Linear Regulator; 0.5um Logic process |
Analog_IP |
0.5um |
Gold |
|
|
REG8003H
|
5V with 150mA driving capability, Istb=120uA Linear Regulator; 0.35um Logic process |
Analog_IP |
0.35um |
Platinum |
|
|
REG8004H
|
5V with 70mA driving capability, Istb=120uA Linear Regulator; 0.35um Logic process |
Analog_IP |
0.35um |
Silver |
|
|
REG9001H
|
3.3V with 70mA driving capability, Istb=75uA Linear Regulator; 0.25um Logic process |
Analog_IP |
0.25um |
Platinum |
|
|
REG9002H
|
3.3V with 150mA driving capability, Istb=75uA Linear Regulator; 0.25um Logic process |
Analog_IP |
0.25um |
Platinum |
|
|
REGA002H
|
3.3V with 100mA driving capability, Istb=100uA Linear Regulator; 0.18um Logic GII process |
Analog_IP |
0.18um |
Gold |
|
|
| |
 |
| |
| Analog > Power |
| > Others |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
FXCHG070HL0A
|
5V to 4.2V battery charger with 3.3V device ; UMC 0.153um Logic/Mixed-Mode Process |
Analog_IP |
0.153um |
Bronze |
|
|
| |
 |
| |
| Analog > Power |
| > Power Management |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
FXCHG010H80U
|
5V to 4.2V battery charger ; UMC 0.35um 3.3V/5V CDMOS Process
|
Analog_IP |
0.35um |
Bronze |
|
|
FXPFM030HR0B
|
3.0V~3.6V to 1.2V DC-DC converter with 100mA driving capability ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
'13Q4 |
|
|
FXPMU001H80U
|
Power Management Unit(5-sets DC-DC, 2-sets REG, PowerSwitch, and Li-ion Charger) for Audio Platform; UMC 0.35um 3.3V/5V CDMOS process |
Analog_IP |
0.35um |
'13Q4 |
|
|
FXPWM010H90A
|
Pulse width modulation, boosting voltage from 3.3V to 5V, 50mA driving capability, Ivcca=150uA @ Idrive=0 |
Analog_IP |
0.25um |
Silver |
|
|
FXPWM010HA0A
|
Pulse width modulation, boosting voltage from 3.3V to 5V, 50mA driving capability, Ivcca=140uA @ Idrive=0 |
Analog_IP |
0.18um |
Gold |
|
|
FXPWM010HC0A
|
PWM controller with soft start function for DC to DC boost converter, 0.13um Logic HS (FSG) process |
Analog_IP |
0.13um |
Platinum |
|
|
FXPWM010HR0B
|
3V~3.6V to 5V DC-DC converter with 100mA driving capability;
UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXPWM011HD0A
|
Boosting voltage from 3.3V to 5V, 100mA driving capability, Ivcca=200uA @ Idrive=0mA, Pulse Width Modulator; UMC 90nm SP/RVT low-K process.
|
Analog_IP |
90nm |
Silver |
|
|
FXPWM011HE0C
|
Boosting voltage from 3.3V to 5V, 100mA driving capability, Ivcca=200uA @ Idrive=0, Pulse Width Modulator; UMC 65nm Logic SP/HVT Low-K process. |
Analog_IP |
65nm |
Silver |
|
|
FXPWM011HE0K
|
DC-DC Power Converter, Input:3.0V~3.6V, output:5V, 50mA loading; UMC 65nm LL(RVT) Low_K process. |
Analog_IP |
65nm |
Bronze |
|
|
FXPWM011HH0L
|
Boosting voltage from 3.3V to 5V, 100mA driving capability, Pulse Width Modulator; UMC 40nm Logic LP/RVT Low-K process. |
Analog_IP |
40nm |
Bronze |
|
|
FXPWM011HL0A
|
Pulse Width Modulation, boosting voltage from 3.3V to 5V/50mA driving capability, Ivcca=140uA@Idrive=0 ; UMC 0.153um Logic/Mixed-Mode Process |
Analog_IP |
0.153um (85% shrink of 0.18um) |
Silver |
|
|
FXPWM020HC0L
|
3.3V to 1.8V high efficiency converter with 150mA driving capability,PWM Regulator; UMC 0.13um Logic LL (FSG) process |
Analog_IP |
0.13um |
Silver |
|
|
FXPWM020HR0B
|
2.5V/3.3V to 1.2V high efficiency converter with 250mA driving capability,PWM Regulator; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
'13Q4 |
|
|
FXPWM021HC0H
|
3.3V to 1.8V high efficiency converter with 200mA driving capability PWM Regulator ; UMC 0.13um HS/FSG Logic Process |
Analog_IP |
0.13um |
Silver |
|
|
FXPWM024HR0B
|
2.5V/3.3V to 1.2V high efficiency converter with 250mA driving capability,Compensation Built-in,PWM Regulator; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
|
Analog_IP |
0.11um |
'13Q4 |
|
|
FXPWM028HR0B
|
2.5V/3.3V to 1.05V high efficiency converter with 250mA driving capability, compensation built-in, PWM regulator;
UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXPWM030H80A
|
Three pulse width modulation, boosting voltage from 3.3V to +/-12.5V, and +6V, Ivcca=450uA @ Idrive=0 |
Analog_IP |
0.35um |
Silver |
|
|
FXPWM030HC0H
|
3.3V to 1.8V high efficiency converter with 150mA driving capability,PWM Regulator; UMC 0.13um HS\FSG Logic Process
|
Analog_IP |
0.13um |
'13Q4 |
|
|
FXPWM050HR0B
|
0.9V~1.6V to 3.0V DC-DC converter with 120mA driving capability for Dry-Battery application; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXPWM052HR0B
|
0.95V~1.5V to 3.0V DC-DC converter with 100mA driving capability ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
Silver |
|
|
FXPWM070HR0B
|
5.0V to 3.3V high efficiency converter with 300mA driving capability PWM Regulator ; UMC 0.11um 1.2V/3.3V HS/AE (AL Advanced Enhancement) Logic Process
|
Analog_IP |
0.11um |
Bronze |
|
|
FXPWM270HR0B
|
2.5v~4.4v to 3.3v/300mA Buck-Boost PWM for Li-ion Battery Application ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
| |
 |
| |
| Analog > Power |
| > Power on Reset |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
FXPORA010HC0H
|
Vrr=0.8V Vfr=0.65V, VCC=1.2V, Ivcc=12.7uA; HS process with A-type I/O.; Power On Reset; UMC 0.13um Logic HS (FSG) process |
Analog_IP |
0.13um |
Gold |
|
|
FXPORA031H90A
|
Power on reset using 0.25um process, A-type I/O ,Urr=1.8V,Ufr=1.6V; UMC 0.25um Logic process. |
Analog_IP |
0.25um |
Gold |
|
|
FXPORAH010HC0H
|
0.13um HS process, 3.3V device vcc3I, Vrr=2.2V, Vfr=2V, Ivcc=13mA; Power On Reset; UMC 0.13um Logic HS (FSG) process |
Analog_IP |
0.13um |
Silver |
|
FXPORAH010HC0H_MBU00 1
|
UMC 0.13um HS Logic process;Vrr=2.2V, without Vfr, A type IO; 3.3V Power On Reset. |
Analog_IP |
0.13um |
Bronze |
|
|
FXPORAH010HR0B
|
Vrr=2.2V, Vfr=2.0V, A type IO; 3.3V Power On Reset; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
|
Analog_IP |
0.11um |
Bronze |
|
|
FXPORAH035HR0F
|
Vrr=2.2V, Vfr=2.0V, A type IO; 3.3V Power On Reset; UMC 0.11um AL eFlash Process |
Analog_IP |
0.11um |
'13Q4 |
|
|
FXPORB010HB0A
|
Vrr=1.1V Vfr=0.95V, VCC=1.5V; B-type I/O.; Power On Reset; UMC 0.15um SP Logic process |
Analog_IP |
0.15um |
Silver |
|
|
FXPORB010HC0H
|
Vrr=0.8V Vfr=0.65V, VCC=1.2V, Ivcc=12.7uA; HS process with B-type I/O.; Power On Reset; UMC 0.13um Logic HS (FSG) process |
Analog_IP |
0.13um |
Gold |
|
|
FXPORB030H90A
|
Vrr=1.8V Vfr=1.6V, VCC=2.5V, Ivcc=13.4uA; B type I/O; Power On Reset; UMC 0.25um Logic process |
Analog_IP |
0.25um |
Gold |
|
|
FXPORB130H90A
|
Power on Reset circuit tolerant with 0.25um,2.5V MMC and Logic process VCC=2.5V, B type IO; Power On Reset; UMC 0.25um Logic process |
Analog_IP |
0.25um |
Gold |
|
|
FXPORBH010HR0B
|
Vrr=2.2V, Vfr=2.0V, A type IO; 3.3V Power On Reset; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXPORBH070HR0B
|
Vrr=2.2V, Vfr=2.0V, B type IO; 3.3V Power On Reset; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
|
Analog_IP |
0.11um |
Bronze |
|
|
FXPORC030HA0A
|
Vrr=1.2V Vfr=1.0V, VCC=1.8V, Ivcc=6.7uA; C type I/O; Power On Reset; UMC 0.18um Logic GII process |
Analog_IP |
0.18um |
Platinum |
|
|
FXPORC130H90A
|
Power on Reset with Vrr and Vfr.; Power On Reset; UMC 0.25um Logic process |
Analog_IP |
0.25um |
Gold |
|
|
FXPORC730HA0L
|
Vrr=1.2V, Vfr=1.1V, C version IO, corner type, Power on Reset ; UMC 0.18um LL process. |
Analog_IP |
0.18um |
Silver |
|
|
FXPORD030HA0A
|
Vrr=1.2V Vfr=1.0V, VCC=1.8V, Ivcc=6.7uA; D type I/O; Power On Reset; UMC 0.18um Logic GII process |
Analog_IP |
0.18um |
Platinum |
|
|
FXPORD130H90A
|
Power on Reset with Vrr and Vfr.; Power On Reset; UMC 0.25um Logic process |
Analog_IP |
0.25um |
Gold |
|
|
FXPORD730HA0A
|
FXPORD730HA0A 0.18um power on reset at the corner of D-type IO Vrr=1.2V Vfr=1V; Power On Reset; UMC 0.18um Logic GII process |
Analog_IP |
0.18um |
Silver |
|
|
FXPORD730HA0L
|
Vrr=1.2V, Vfr=1.1V, D version IO, corner type, Power on Reset; UMC 0.18um LL process. |
Analog_IP |
0.18um |
Bronze |
|
|
FXPORK010HD0K
|
Power On Reset (POR); UMC 90nm LL logic process, RVT; Core type; Vrr=0.85V Vfr=0.75V. |
Analog_IP |
90nm |
Bronze |
|
|
FXPORK030HA0A
|
Vrr=1.2V Vfr=1.0V, VCC=1.8V, Ivcc=6.7uA; Core type; Power On Reset; UMC 0.18um Logic GII process. |
Analog_IP |
0.18um |
Platinum |
|
|
FXPORK030HA0L
|
Vrr=1.2V Vfr=1.1V, VCC=1.8V, Ivcc=12.2uA; Core type; Power On Reset; UMC 0.18um Logic LL process. |
Analog_IP |
0.18um |
Bronze |
|
|
FXPORK030HC0H
|
Vrr=0.8V Vfr=0.65V, VCC=1.2V, Ivcc=11.7uA; Core type; Power On Reset; UMC 0.13um logic HS(FSG) process. |
Analog_IP |
0.13um |
ASIC Silver |
|
|
FXPORK030HC0L
|
Vrr=0.8V Vfr=0.65V, VCC=1.2V, Ivcc=10.7uA; Core type; Power On Reset; UMC 0.13um Logic LL(FSG) process. |
Analog_IP |
0.13um |
Platinum |
|
|
FXPORK030HE0L
|
Vrr=Vfr=0.8V,input VCC=1.2V, 1.2V Power On Reset; UMC 65nm 1P10M2T LP/RVT LowK Logic Process
|
Analog_IP |
65nm |
Bronze |
|
|
FXPORK030HF0L
|
Vrr=Vfr=0.8V,input VCC=1.2V, 1.2V Power On Reset; UMC 55nm 1P10M2T LP/RVT LowK Logic Process |
Analog_IP |
55nm |
'13Q4 |
|
|
FXPORK035HA0A
|
Vrr=1.2V Vfr=1.0V, input 1.8V, Core type; Power On Reset; UMC 0.18um Logic GII process |
Analog_IP |
0.18um |
Bronze |
|
|
FXPORK035HD0K
|
Vrr=0.7V, Vfr=0.65V, input VCCK=1.2V, Core Type Power On Reset; UMC 90nm Logic/Mixed-mode LL-RVT LowK Process
|
Analog_IP |
90nm |
Bronze |
|
|
FXPORK035HE0A
|
Vrr=0.67V, Vfr=0.62, input 10V, Core type; Power On Reset; UMC 65nm SP/RVT LowK Process
|
Analog_IP |
65nm |
Silver |
|
|
FXPORK035HF0A
|
Vrr=0.67V, Vfr=0.62, input 10V, Core type; Power On Reset; UMC 55nm SP/RVT LowK Process
|
Analog_IP |
55nm |
Bronze |
|
|
FXPORK050H90A
|
Vrr=1.6V Vfr=1.4V, core type; Power On Reset with tunable reset time by external capacitor; UMC 0.25um Logic/MMC process |
Analog_IP |
0.25um |
Gold |
|
|
FXPORK050HA0A
|
Vrr=1.2V Vfr=1.0V, input 1.8V, Core type; Power On Reset; UMC 0.18um GII process |
Analog_IP |
0.18um |
Bronze |
|
|
FXPORK055HA0A
|
Vrr=1.2V Vfr=1.0V, input 1.8V, Core type (with Self-Test Circuit); Power On Reset; UMC 0.18um GII process
|
Analog_IP |
0.18um |
ASIC Silver |
|
|
FXPORK055HL0A
|
Vrr=1.2V Vfr=1.0V, input 1.8V, Core type (with Self-Test Circuit); Power On Reset; UMC 0.153um Mixed-Mode/Logic Process |
Analog_IP |
0.153um |
Bronze |
|
|
FXPORK055HP0A
|
Vrr=1.2V Vfr=1.0V, input 1.8V, Core type (with Self-Test Circuit); Power On Reset; UMC 0.162um Logic Process
|
Analog_IP |
0.162um |
ASIC Silver |
|
|
FXPORK130H80A
|
Vrr=1.96V Vfr=1.76V, input 3.3V, Core Type; Power On Reset; UMC 0.35um Logic process |
Analog_IP |
0.35um |
Bronze |
|
|
FXPORK130HA0F
|
Vrr=1.2V Vfr=1.0V, input 1.8V, Core type; Power On Reset; UMC 0.18um e-Flash process |
Analog_IP |
0.18um |
Silver |
|
|
FXPORK130HC0G
|
Vrr=0.76V Vfr=0.66V, input 1.2V, Core type; Power On Reset; UMC 0.13um Logic SP(FSG) process |
Analog_IP |
0.13um |
Silver |
|
|
FXPORK130HC0H
|
Vrr=0.75V Vfr=0.65V, input 1.2V, Core type; Power On Reset; UMC 0.13um Logic HS(FSG) process |
Analog_IP |
0.13um |
Bronze |
|
|
FXPORK135HC0G
|
Vrr=0.76V Vfr=0.66V, input 1.2V, Core type; Power On Reset; UMC 0.13um Logic SP(FSG) process |
Analog_IP |
0.13um |
Bronze |
|
|
FXPORK135HC0H
|
Vrr=0.75V Vfr=0.65V, input 1.2V, Core type; Power On Reset; UMC 0.13um Logic HS(FSG) process |
Analog_IP |
0.13um |
ASIC Silver |
|
|
FXPORK135HD0A
|
Vrr=0.67V Vfr=0.63V, input 1.0V, Core type; Power On Reset (with Self-Test Circuit);UMC 90nm Logic SP-RVT LowK process
|
Analog_IP |
90nm |
Gold |
|
|
FXPORK235HP0U
|
Power on reset(POR) block ; UMC 0.162um EHV Process |
Analog_IP |
0.162um |
Bronze |
|
|
FXPORK235HR0B
|
Power on reset(POR) block ; UMC 0.11um HS/AE (AL Advance Enhancement) Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXPORK235HR0H
|
Power on reset(POR) block; UMC 0.11um HS/copper Logic Process |
Analog_IP |
0.11um |
ASIC Silver |
|
|
FXPORKH075HD0A
|
Vrr=Vfr=2V,input VCC3IO=3.3V, 3.3V RTC Power On Reset;special request by MTD; UMC 90nm 1P9M2T SP/RVT LowK Logic Process
|
Analog_IP |
90nm |
Bronze |
|
|
FXPORKH075HF0A
|
3.9~1.5V (RTC core cell operating voltage+), Rise-relax voltage (Vrr), min. 1.6V (1.6V~2.3V) Power On Reset ; UMC 55nm SP/RVT LowK Logic Process
|
Analog_IP |
55nm |
Bronze |
|
|
FXPORKH075HH0L
|
Vrr=2.0V Vfr=1.9V, VCC3I=2.5V, 2.5V Power On Reset;special request; UMC 40nm LP/RVT LowK Logic Process |
Analog_IP |
40nm |
'13Q4 |
|
|
FXPORKLH035HC0H
|
2.5V~3.3V POR ; UMC 0.13um HS/FSG Logic Process |
Analog_IP |
0.13um |
Bronze |
|
|
FXPORKLH035HD0A
|
Vrr=2V Vfr=1.95V, input VCCK=1.0V VCC3IO=3.3V, 3.3V Power On Reset;special request by ASAL; UMC 90nm 1P9M SP/RVT LowK Logic Process |
Analog_IP |
90nm |
Bronze |
|
|
FXPORKLH035HH0L
|
Vrr=2.33V Vfr=2.26V, input VCCK=1.0V VCC3IO=3.3V, 3.3V Power On Reset;special request; UMC 40nm LP/RVT LowK Logic Process
|
Analog_IP |
40nm |
Bronze |
|
|
POR7002
|
Vrr=3.4V Vfr=3.0V, VCC=5V, Ivcc=17uA; B type I/O; Power On Reset; UMC 0.5um Logic process |
Analog_IP |
0.5um |
Gold |
|
|
POR8001
|
Vrr=2.5V Vfr=2.3V, VCC=3.3V, Ivcc=18uA; Power On Reset; UMC 0.35um Logic process |
Analog_IP |
0.35um |
Platinum |
|
|
PORB030HA0A
|
Vrr=1.2V Vfr=1.0V, VCC=1.8V, Ivcc=6.7uA; B type I/O; Power On Reset; UMC 0.18um Logic GII process |
Analog_IP |
0.18um |
Gold |
|
|
PORM3B
|
Vrr=2.3V without Vfr, VCC=3.3V, Ivcc=17uA; B type I/O; Power On Reset; UMC 0.5um Logic process |
Analog_IP |
0.5um |
Gold |
|
|
PORM3L
|
Vrr=2.3V without Vfr, VCC=3.3V, Ivcc=17uA; L type I/O; Power On Reset; UMC 0.5um Logic process low voltage |
Analog_IP |
0.5um |
Gold |
|
|
| |
 |
| |
| Analog > Power |
| > Switching Regulator |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
FXREG021HR0B
|
Input 2.7V-3.6V, 1.2V/10mA Output Regulator; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
| |
 |
| |
| Analog > Power |
| > Voltage Dectector |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
FXVDT010HA0A
|
Vdet=1.3V Vhys=0.1V, VCCA=1.8V, Ivcca=35uA; UMC 0.18um Logic GII process |
Analog_IP |
0.18um |
'13Q4 |
|
|
FXVDT010HR0H
|
Voltage Detect Vdet=2.5V Vhys=0.1V, generate a high/low level logic for a precise power supply monitoring system;
UMC 0.11um HS/FSG Logic Process |
Analog_IP |
0.11um |
Bronze |
|
|
FXVDT020HA0A
|
4-level detector for USB-OTG, VCCA=3.3V, Ivcca=125uA; UMC 0.18um Logic GII process |
Analog_IP |
0.18um |
Platinum |
|
|
FXVDT020HC0A
|
4-level voltage detector for USB_OTG; UMC 0.13um Logic HS (FSG) process |
Analog_IP |
0.13um |
Platinum |
|
|
FXVDT020HR0B
|
4-level detector for USB-OTG applications, input 3.3V; UMC 0.11um HS/AE Logic process |
Analog_IP |
0.11um |
Bronze |
|
|
FXVDT020HR0F
|
4-level detector for USB-OTG applications, input 3.3V; UMC 0.11um eFlash Logic process
|
Analog_IP |
0.11um |
'13Q4 |
|
|
FXVDT021HD0A
|
4-Level Voltage Detector for USB-OTG; UMC 90nm Lgic SP-RVT (LowK) process and 2.5V overdrive 3.3V device. |
Analog_IP |
90nm |
Silver |
|
|
FXVDT021HD0K
|
4-Level Voltage Detector for USB-OTG; UMC 90nm logic LL-RVT (LowK) process and 2.5V overdrive 3.3V device. |
Analog_IP |
90nm |
Silver |
|
|
FXVDT021HE0C
|
4-Level Voltage Detector for USB-OTG (2.5V overdrive 3.3V device); UMC 65nm logic SP-HVT (LowK) process
|
Analog_IP |
65nm |
Silver |
|
|
FXVDT021HE0K
|
4-Level Voltage Detector for USB-OTG; UMC 65nm logic LL-RVT (LowK) process and 2.5V overdrive 3.3V device. |
Analog_IP |
65nm |
Silver |
|
|
FXVDT021HF0A
|
4-Level Voltage Detector for USB-OTG ; UMC 55nm 2.5V overdrive 3.3V device SP/HVT LowK Logic Process |
Analog_IP |
55nm |
Bronze |
|
|
FXVDT021HH0L
|
4-Level Voltage Detector for USB-OTG ; UMC 40nm 2.5V overdrive 3.3V device LP/RVT Logic Process |
Analog_IP |
40nm |
Bronze |
|
|
FXVDT021HL0A
|
4-level detector for USB-OTG, VCCA=3.3V, Ivcca=125uA; UMC 0.153um 1.8V/3.3V Logic GII process |
Analog_IP |
0.153um (85% shrink of 0.18um) |
Silver |
|
|
FXVDT040H90A
|
0.25um process 2 level voltage detector; UMC 0.25um Logic process |
Analog_IP |
0.25um |
Silver |
|
|
FXVDT040HA0A
|
3-level detector for MMC flash storage, VCCA=3.3V, Ivcca=65uA; UMC 0.18um Logic GII process |
Analog_IP |
0.18um |
'13Q4 |
|
|
FXVDT040HA0L
|
VDT for MMC; UMC 0.18um Logic LL process |
Analog_IP |
0.18um |
Silver |
|
|
FXVDT050HA0A
|
4-level voltage detector for MP3; UMC 0.18um Logic GII process |
Analog_IP |
0.18um |
Silver |
|
|
FXVDT050HC0L
|
4-level voltage detector , input 1.2V, Ivcca=65uA; UMC 0.13um LL-LVT(FSG) process. |
Analog_IP |
0.13um |
'13Q4 |
|
|
FXVDTH030H90A
|
Vdet=2.8V Vhys=0.1V, VCCA=3.3V, Ivcca=30uA; UMC 0.25um Logic process |
Analog_IP |
0.25um |
Platinum |
|
|
FXVDTH030HA0A
|
Vdet=2.4V, Vhys=0.1V, VCCA=3.3V, Ivcca=35uA; UMC 0.18um Logic GII process |
Analog_IP |
0.18um |
Gold |
|
|
FXVDTH030HA0L
|
Voltage detector for flash protect; UMC 0.18um Logic LL process |
Analog_IP |
0.18um |
Silver |
|
|
FXVDTL010H70A
|
5V/3.3V detector VDT; UMC 0.5um Logic process |
Analog_IP |
0.5um |
Gold |
|
|
VDT030H80A
|
Vdet=2.55V Vhys=0.05V, VCC=3.3V, Ivcc=35uA; UMC 0.35um Logic process |
Analog_IP |
0.35um |
Gold |
|
|
VDT9001
|
Vdet=2.1V Vhys=0.1V, VCCA=2.5V, Ivcca=27uA; UMC 0.25um Logic process |
Analog_IP |
0.25um |
Gold |
|
|
| |
 |
| |
| Analog > Serial Link PHY |
| > 10/100 Ethernet PHY |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
FXEDP110HC0A
|
10/100 Base-TX Fast Ethernet PHY; UMC 0.13um Logic HS (FSG) process. |
Analog_IP |
0.13um |
Gold |
|
|
FXEDP110HD0A
|
10/100 Base-TX Fast Ethernet PHY; UMC 90nm SP/RVT Low-K Logic Process
|
Analog_IP |
90nm |
'13Q4 |
|
|
FXEDP110HE0A
|
10/100 Base-TX Fast Ethernet PHY; UMC 65nm SP/RVT Low-K Logic Process
|
Analog_IP |
65nm |
'13Q4 |
|
|
FXEDP110HH0L
|
10/100 Base-TX Energy Efficient Ethernet PHY; UMC 40nm LP/RVT Low-K Logic Process |
Analog_IP |
40nm |
'13Q4 |
|
|
FXEDP112HA0A
|
10/100 Base-TX Fast Ethernet PHY; UMC 0.18um MMC process. |
Analog_IP |
0.18um |
'13Q4 |
|
|
FXEDP118HR0B
|
10/100 Base-TX/FX Energy Efficient Ethernet PHY; UMC 0.11um HS/AE (AL Advance Enhancement) Logic Process.
|
Analog_IP |
0.11um |
Bronze |
|
|
FXEDP118HR0F
|
10/100 Base-TX/FX Energy Efficient Ethernet PHY; UMC 0.11um eFlash Logic Process. |
Analog_IP |
0.11um |
'13Q4 |
|
|
FXFEP160H90A
|
10/100 Base-TX Ethernet PHY; UMC 0.25um Logic process. |
Analog_IP |
0.25um |
Gold |
|
|
| |
 |
| |
| Analog > Serial Link PHY |
| > PCI Express PHY |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
FXPCIE100HA0A
|
PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY; UMC 0.18um Logic GII (RVT) process |
Analog_IP |
0.18um |
Bronze |
|
|
FXPCIE166HA0A
|
PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY; UMC 0.18um Logic GII (RVT) process |
Analog_IP |
0.18um |
Bronze |
|
|
FXPCIE169HC0H
|
PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY with low power feature; UMC 0.13um HS/FSG Logic Process |
Analog_IP |
0.13um |
'13Q4 |
|
|
FXPCIE200HD0A
|
PCI-Express II PHY; UMC 90nm SP/RVT Low-K Process |
Analog_IP |
90nm |
'13Q4 |
|
|
FXPCIE268HE0L
|
PCIE Gen.II PHY; UMC 65nm LP/RVT LowK Logic Process. |
Analog_IP |
65nm |
'13Q4 |
|
|
FXPCIE268HF0A
|
PCIE Gen.II ; UMC 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
Silver |
|
|
FXPCIE4X200HD0A
|
4x lane PCI Express Gen II PHY; UMC 90nm SP/RVT Low-K Logic Process |
Analog_IP |
90nm |
'13Q4 |
|
|
| |
 |
| |
| Analog > Serial Link PHY |
| > Serial ATA PHY |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
FXESATA303HA0A
|
1.5G/3.0Gbps 1 port Serial ATA PHY and ESATA ; UMC 0.18um Logic GII process. |
Analog_IP |
0.18um |
'13Q4 |
|
|
FXSATA168HC0H
|
3G/1.5G Serial ATA PHY; UMC 0.13um HS/FSG Logic Process |
Analog_IP |
0.13um |
Gold |
|
|
FXSATA168HD0A
|
Serial ATA I II PHY;UMC 90nm SP/RVT Lowk Logic Process |
Analog_IP |
90nm |
ASIC Silver |
|
|
FXSATA168HR0B
|
3G/1.5G Serial ATA PHY; UMC 0.11um HS/AE (AL Advance Enhancement) Logic Process
|
Analog_IP |
0.11um |
Silver |
|
|
FXSATA168HR0H
|
3G/1.5G Serial ATA PHY; UMC 0.11um HS/FSG Logic Process |
Analog_IP |
0.11um |
Gold |
|
|
FXSATA1X300HC0H
|
Serial ATA (SATA) physical layer that provides a complete range of host and device functions; UMC 0.13um Logic HS(FSG) process |
Analog_IP |
0.13um |
Bronze |
|
|
FXSATA1X310HC0U
|
Over sampling 1 port 3G/1.5G SATA PHY ; UMC 0.13um HS+LL/FSG Logic Process |
Analog_IP |
0.13um |
Bronze |
|
|
FXSATA268HF0A
|
Serial ATA I,II PHY ;UMC 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
'13Q4 |
|
|
FXSATA301HA0A
|
Single channel serial ATA PHY layer compliant with SATA spec. of 3.0 Gbps. |
Analog_IP |
0.18um |
'13Q4 |
|
|
FXSATA368HF0A
|
Serial ATA I,II,III PHY ; UMC 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
Bronze |
|
|
FXSATA368HR0H
|
6G/3G/1.5G Serial ATA PHY; UMC 0.11um HS/FSG Logic Process
|
Analog_IP |
0.11um |
'13Q4 |
|
|
FXSERDES101HH0L
|
10Gbps SERDES for 10Gbase-kr application,UMC 40nm LP/RVT Logic Process |
Analog_IP |
40nm |
'13Q4 |
|
|
| |
 |
| |
| Analog > Serial Link PHY |
| > USB 1.1 PHY |
| Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
|
FZUSB100H70A
|
USB 1.1 PHY ; UMC 0.5um Logic process 3.3V 1P3M |
Analog_IP |
0.5um |
Silver |
|
|
FZUSB100HA0A
|
USB 1.1 PHY; UMC 0.18um GII process 1.8/3.3V 1P6M
|
Analog_IP |
0.18um |
Gold |
|
|
FZUSB100HA0F
|
USB 1.1 PHY; UMC 0.18um e-flash process
|
Analog_IP |
0.18um |
Silver |
|
|
FZUSB100HC0H
|
USB 1.1 PHY; UMC 0.13um Logic HS (FSG) process. |
| | |