Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
FXLVDS168HR0H
|
Low power LVDS Receiver IO 50Mbps; UMC 0.11 um Logic HS/FSG (Cu) Process |
Analog_IP |
0.11um |
Contact Sales
|
|
FXLVDSRX060HH0L
|
LVDS RX,UMC 40nm LP/RVT LowK Logic Process |
Analog_IP |
40nm |
Silver
|
|
FXLVDSRX080HH0L
|
LVDS RX IO PAD 500 Mbps ,UMC 40nm LP/RVT LowK Logic Process
|
Analog_IP |
40nm |
Contact Sales
|
|
FXLVDSRX080HH0L_BUMP
|
LVDS RX IO PAD 500 Mbps, UMC 40nm LP/RVT LowK Logic Process, Bump pad. |
Analog_IP |
40nm |
Contact Sales
|
|
FXLVIORX800HH0L
|
1.8v LVDS RX IO 800Mbps, UMC 40nm LP/RVT LowK Logic Process |
Analog_IP |
40nm |
Contact Sales
|
|
FXLVRX012HC0H
|
DLL-based LVDS RX; VCC=3.3 for 20M~135MHz and VCC=2.5 for 20M~100MHz operation freq. 1data(581Mbps) +1clock(83Mhz).
UMC 0.13um HS FSG Logic Process |
Analog_IP |
0.13um |
Contact Sales
|
|
FXLVRX015HC0H
|
DLL-based LVDS RX,VCC=3.3V for 11.5MHz ~ 34.6MHz operation frequency, UMC 0.13um HS FSG Logic Process
|
Analog_IP |
0.13um |
Contact Sales
|
|
FXLVRX020HA0A
|
0.18UM RX (PAD); UMC 0.18um GII Process |
Analog_IP |
0.18um |
Silver
|
|
FXLVRX020HC0H
|
0.13um LVDS RX I/O PAD; UMC 0.13um HS HVT-FSG Process. |
Analog_IP |
0.13um |
Silver
|
|
FXLVRX020HD0A
|
2.5V LVDS Receiver 8~135MHz; 90nm SP process
|
Analog_IP |
90nm |
Silver
|
|
FXLVRX020HH0L
|
3.3v LVDS RX,UMC 40nm LP/RVT LowK Logic Process |
Analog_IP |
40nm |
Contact Sales
|
|
FXLVRX020HJ0C
|
LVDS RX Receives serial LVDS signal and de-serialize them into parallel format ; UMC 28nm HPC Logic Process |
Analog_IP |
28nm |
Contact Sales
|
|
FXLVRX020HJ0P
|
UMC 28nm HPC+ Logic Process, LVDS RX Receives serial LVDS signal and de-serialize them into parallel format |
Analog_IP |
28nm |
Contact Sales
|
|
FXLVRX020HR0B
|
Low power LVDS Receiver 800Mbps; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
|
Analog_IP |
0.11um |
Contact Sales
|
|
FXLVRX023HF0A
|
DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
Contact Sales
|
|
FXLVRX024HF0A
|
55nm-SP, FPD-Link Receiver, 3.3V/1.0V, 4 data plus 1 clock channel, 16~85MHz, DLL type, |
Analog_IP |
55nm |
Contact Sales
|
|
FXLVRX025HF0A
|
DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process
|
Analog_IP |
55nm |
Contact Sales
|
|
FXLVRX030HF0A
|
Low power LVDS Receiver IO 500Mbps; UMC 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
Silver
|
|
FXLVRX030HH0L
|
3.3v LVDS RX, 3 data lane and 1 clock lane using UMC 40nm LP/RVT LowK Logic Process |
Analog_IP |
40nm |
Bronze
|
|
FXLVRX038HH0L
|
8 Lanes LVDS RX IO PAD, UMC 40nm LP/RVT LowK Logic Process |
Analog_IP |
40nm |
Contact Sales
|
|
FXLVRX050HH0L
|
3.3v LVDS RX IO 1.25Gbps, UMC 40nm LP/RVT LowK Logic Process |
Analog_IP |
40nm |
Contact Sales
|
|
FXLVRX060HC0H
|
DLL-based LVDS RX; VCC=3.3 for 20M~135MHz and VCC=2.5 for 20M~100MHz operation freq.; UMC 0.13um HS FSG Logic Process |
Analog_IP |
0.13um |
Silver
|
|
FXLVRX060HD0A
|
Low power LVDS Receiver 700Mbps ; UMC 90nm SP/RVT Lowk Logic Process |
Analog_IP |
90nm |
Silver
|
|
FXLVRX060HF0A
|
DLL-based LVDS RX ; 55nm SP/RVT LowK Logic Process |
Analog_IP |
55nm |
Silver
|
|
FXLVRX080HD0A
|
LVDS RX IO ; UMC 90nm SP/RVT LowK Logic Process |
Analog_IP |
90nm |
Silver Minus
|
|
FXLVRX080HF0F
|
LVDS RX IO PAD 300 Mbps with combo GPIO , UMC 55nm eflash/RVT LowK Logic Process |
Analog_IP |
55nm |
Silver
|
|
FXLVRX080HF0L
|
LVDS RX IO PAD 500 Mbps ,UMC 55nm LP/RVT LowK Logic Process |
Analog_IP |
55nm |
Silver
|
|
FXLVRX080HH0L
|
LVDS RX IO PAD 500 Mbps, UMC 40nm LP/RVT LowK Logic Process, for flip chip |
Analog_IP |
40nm |
Contact Sales
|
|
FXLVRX082HC0H
|
20M~135MHz DLL-based LVDS RX; UMC 0.13um HS/FSG Process |
Analog_IP |
0.13um |
Silver
|
|
FXLVRX4312HF0A
|
4-Data Channel DLL-based LVDS RX ; 55nm SP/RVT LowK Logic Process ; 3.3V IO / 1.0V Core ; Clock Range 10Mhz~180Mhz |
Analog_IP |
55nm |
Contact Sales
|
|
FXLVRX5308HH0L
|
5-Data Channel DLL-based LVDS RX ; 40LP/RVT low-K process ; 3.3V IO / 1.1V Core ; Clock Range 16Mhz~120Mhz
|
Analog_IP |
40nm |
Contact Sales
|
|
FXLVRXBS050HH0L
|
The bias block only for FXLVRX050HH0L, UMC 40nm LP/RVT LowK Logic Process |
Analog_IP |
40nm |
Contact Sales
|
|
FXLVRXBS080HF0F
|
The bias block only for FXLVRX080HF0F, UMC 55nm eflash/RVT LowK Logic Process |
Analog_IP |
55nm |
Contact Sales
|
|
FXLVRXBS080HF0L
|
The bias block only for FXLVRX080HF0L, UMC 55nm LP/RVT LowK Logic Process |
Analog_IP |
55nm |
Contact Sales
|
|
FXLVRXBS080HH0L
|
The bias block only for FXLVDSRX080HH0L, UMC 40nm LP/RVT LowK Logic Process |
Analog_IP |
40nm |
Contact Sales
|
|