DDR

Updated On:2018-01-19
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Interface Solution > DDR
 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3A50225EWHJ0L Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY Horizontal version; UMC 28nm HLP Logic and Mixed-Mode Process Analog_IP 28nm Contact Sales
 
FXDDR3A50225NSHJ0L Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY Vertical version; UMC 28nm HLP Logic and Mixed-Mode Process Analog_IP 28nm Contact Sales
 
FXDDR3D50225EWHJ0L Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY Horizontal version; UMC 28nm HLP Logic and Mixed-Mode Process Analog_IP 28nm Contact Sales
 
FXDDR3D50225NSHJ0L Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY Vertical version; UMC 28nm HLP Logic and Mixed-Mode Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > DDR
> DDR Controller > DDR3 - Addresss/Command  
Cell Name Descriptions Type Process Gradation Literature
FXDDR3PHYA100EWHJ0C DDR3 RTL Digitalize PHY AC block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS Analog_IP 28nm Contact Sales
 
Interface Solution > DDR
> DDR Controller > DDR3 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3PHYD100NSHJ0C DDR3 RTL Digitalize PHY DATA block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS Analog_IP 28nm Contact Sales
 
Interface Solution > DDR
> DDR IO > DDR1 - SSTL2 IO Library 
Cell Name Descriptions Type Process Gradation Literature
FOA0A_A33_TMVH33L25_
SSTL2C1WLVTTL_IO
UMC 0.18um GII Logic Process SSTL2 ClassI with 3.3V LVTTL combo IO Cell Library Library_Group 0.18um Silver
 
FOA0A_A33_TMVH33L25_
SSTL2C2WLVTTL_IO
UMC 0.18um GII Logic Process SSTL2 ClassII IO group with 3.3V LVTTL combo IO Cell Library Library_Group 0.18um Silver
FOA0A_O_TMVH33L25_SS
TL2C1WLVTTL_IO
UMC 0.18um GII Logic Process 2.5/3.3V SSTL2 ClassI/LVTTL combo IO with POC solution Library_Group 0.18um Silver
FOA0A_O_TMVH33L25_SS
TL2C2WLVTTL_IO
UMC 0.18um GII Logic Process 2.5V/3.3V SSTL2 Class II/LVTTL combo IO with POC solution Library_Group 0.18um Silver
FOC0H_A33_TMVH33L25_
SSTL2C1WLVTTL_IO
UMC 0.13um process,SSTL-2 (ClassI)/LVTTL (10mA) Combo I/O Cells; This IP is branched from 'FSC0H_D_TMVH33L25_SSTL2C1WLVTTL_IO'. Library_Group 0.13um Silver
FOC0H_A33_TMVH33L25_
SSTL2C2WLVTTL_IO
UMC 0.13um Logic Process,Specification for SSTL-2 Class-II and LVTTL Combo IO; This IP is branched from 'FSC0H_D_TMVH33L25_SSTL2C2WLVTTL_IO' Library_Group 0.13um Silver
FOC0H_B33_TMVH33VL25
V_SSTL2C1WLVTTL_IO
UMC 0.13um HS/FSG Logic Process Ultra-slim SSTL-2 (ClassI)/LVTTL (10mA) Combo I/O Cells Library_Group 0.13um Contact Sales
 
FOC0H_O33_TMVH33L25_
SSTL2C1WLVTT
UMC 0.13um HS/FSG SSTL2 (class 1) IO for BOAC Library_Group 0.13um Silver
FOC0H_O33_TMVH33L25_
SSTL2C2WLVTT
UMC 0.13um HS/FSG Logic Process 2.5V/3.3V SSTL2-Class II/LVTTL combo IO with POC solution Library_Group 0.13um Silver
FOC0H_P33_T25_SSTL2C
1_IO
UMC 0.13um HS/FSG Logic Process SSTL-2 (ClassI) mini BOAC I/O Cells Library_Group 0.13um Bronze
FOD0A_O25_T25_SSTL2C
1_IO
UMC 90nm SP/Low-K Logic Process SSTL-2 (ClassI) BOAC I/O Cells Library_Group 90nm Bronze
 
FOR0B_O33_TMVH25L18_
SSTL2WMDDR_IO
UMC 0.11um AE/HS Logic Process DD1/DDR2 combo MDDR IO Cell Library Library_Group 0.11um Bronze
FS90A_B_T25_SSTL2_IO UMC 0.25um LOGIC process true 2.5V SSTL-2 IO cells Library_Group 0.25um Silver
 
FS90A_B_TMVH33L25_SS
TL2C1WLVTTL_IO
UMC 0.25um process SSTL2 ClassI with 3.3V LVTTL combo. Library_Group 0.25um Silver
 
FSA0A_C_T25_SSTL2_IO UMC 0.18um GII process true 2.5V SSTL-2 IO cells Library_Group 0.18um Silver
FSA0A_C_TMVH33L25_SS
TL2C1WLVTTL_IO
UMC 0.18um process SSTL2 ClassI with 3.3V LVTTL combo Library_Group 0.18um Silver
FSA0A_C_TMVH33L25_SS
TL2C2WLVTTL_IO
UMC 0.18um process ,SSTL2 ClassII IO group with 3.3V LVTTL combo. Library_Group 0.18um Silver
FSB0G_A_TMVH33L25_SS
TL2C2WLVTTL_IO
UMC 0.15um SP process standard Multi-Voltage High 3.3V Low 2.5V SSTL-2 class-II with LVTTL IO cells. Library_Group 0.15um Silver
 
Interface Solution > DDR
> DDR IO > DDR2 - SSTL18 IO Library 
Cell Name Descriptions Type Process Gradation Literature
FOC0H_O33_TMVH25L18_
SSTL18AWSSTL2C1_IO
UMC, 0.13um Logic HS/FSG process SSTL(2.5V) & SSTL18 (1.8V) combo IO Library_Group 0.13um Bronze
 
FOD0A_B25_T18_SSTL18
AWLVCMOS18_IO
UMC 90nm SP RVT process SSTL18 IO cell library Library_Group 90nm Contact Sales
 
FOF0L_PRS25_TMVH25L1
8_SSTL2WPWL_IO
55LP DDR1/DDR2 IO. 1. U55 LP Process 2. DDR2/DDR1 IO -2.5V SSTL2/1.8 SSTl18 ( CMOS/SSTL) –4 Driving strength @ Target: DDR 533 Mbps( IO 266 MHz) -VCCK Core power-off, All IO pull low Library_Group 55nm Contact Sales
 
 
Interface Solution > DDR
> DDR IO > DDR3 - POD IO 
Cell Name Descriptions Type Process Gradation Literature
FOJ0L_QRS25_T15_DDR3
WPOD_IO
UMC 28nm HLP/RVT Low-K Logic process true 1.5V DDR3 with 2.5V Device IO cell Library Library_Group 28nm Contact Sales
 
 
Interface Solution > DDR
> DDR IO > MDDR IO Library 
Cell Name Descriptions Type Process Gradation Literature
FOC0H_A33_T18_MDDR_I
O
UMC 0.13um HS/FSG Process High speed 1.2/3.3V Process Mobil DDR IO Group Library_Group 0.13um Bronze
FOC0H_O33_T18_MDDR_I
O
UMC 0.13um HS/FSG Logic Library (core) 1.8V MDDR IO with POC solution Library_Group 0.13um Bronze
FOD0K_B25_T18_MDDR_B
_IO
UMC 90nm Logic LL-RVT process 2.5V standard IO cell Library (Version B MDDR IO) Library_Group 90nm Silver
 
Interface Solution > DDR
> DDR PHY - Combo > DDR3/3L - Combo Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3LTA102HH0L DDR3/DDR3L/LPDDR2 combo PHY ( not support DDR3 leveling function), command / address block,UMC 40nm LP/RVT LowK Logic Process. Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR1 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR1A173HF0A DDR1/MDDR PHY CMD/ADDR BLOCK ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process Analog_IP 55nm Bronze
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR2 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR2A173HE0A DDR2/MDDR PHY CMD/ADDR BLOCK ; UMC 65nm 1.0V process with 2.5V device SP/RVT Lowk Logic Process Analog_IP 65nm Silver
FXDDR2A173HF0A DDR2/MDDR Combo PHY CMD ADDR block ; UMC 55nm SP/RVT Lowk Process with 2.5V device Analog_IP 55nm Silver
FXDDR2A174HE0A DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage ; UMC 65nm 1.0V with 2.5V Device SP/RVT LowK Logic Process Analog_IP 65nm Silver
FXDDR2A174HF0A DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage; UMC 55nm 1.0V with 2.5V device SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR2A200HC0H DDR2/MDDR Combo Command/Address Block ; UMC 0.13um HS/FSG Logic Process Analog_IP 0.13um Bronze
FXDDR2A200HE0L DDR2/DDR1/MDDR Combo Command/Address Block ; UMC 65nm LP/RVT LowK Logic Process Analog_IP 65nm Silver
FXDDR2A200HR0B Command/address block of 1:2 DDR2-PHY ; 0.11um HS/AE (AL Advanced Enhancement) Logic Process Analog_IP 0.11um Silver Minus
FXDDR2A200HR0H 1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process Analog_IP 0.11um Silver
 
FXDDRIIA171HC0H DDR2 PHY Command/Address Block ; UMC 0.13um HS/FSG Logic Process Analog_IP 0.13um Platinum
FXDDRIIA172HC0H DDR2 PHY Command/Address Block (for Chip Application); UMC 0.13um HS/FSG Logic Process Analog_IP 0.13um Silver
FXDDRIIA173HD0A_FTC DDR2-PHY command/address block for DRAM chip, BOAC ; UMC 90nm SP/RVT Low-K Logic Process Analog_IP 90nm Silver Minus
FXDDRIIA174HD0A DDR2-PHY Command/Address block; UMC 90nm SP/RVT Lowk Process Analog_IP 90nm Gold
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR3 PHY - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3AIO502EWHJ0C_F
TC
IO Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR ; UMC 28nm HPC/RVT Logic Process Analog_IP 28nm Contact Sales
 
FXDDR4AFC602HH0L Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR3/3L - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3A100HD0A DDR2/3 Combo Command /Address Block (with 2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Process Analog_IP 90nm Silver Minus
FXDDR3A100HH0L DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device Analog_IP 40nm Silver
FXDDR3A300HF0A Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3A300HF0L Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Silver Minus
FXDDR3A402HF0A Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3A403HF0A Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application;UMC 55nm SP/RVT LowK PROCESS. Analog_IP 55nm Silver
FXDDR3A412HF0L Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Bronze
FXDDR3A502HF0A Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Contact Sales
 
FXDDR3A502HH0L Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process Analog_IP 40nm Silver
FXDDR3A503HH0L DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
FXDDR3AFC502HH0L DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR4 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4AFC101HH0L DDR34 COMBO PHY ADDR Block for Solder bump Flip chip version ;UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
FXDDR4AFD612EWHJ0C Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version ; UMC 28nm Logic and Mixed-Mode Low-K HPC Process Analog_IP 28nm Contact Sales
 
FXDDR4AFD612HH0L Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version; UMC 40nm LP LVT/RVT LowK Logic Process Analog_IP 40nm Contact Sales
FXDDR4AFD612NSHJ0C Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version ; UMC 28nm Logic and Mixed-Mode Low-K HPC Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > LPDDR2 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3A412HF0A Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Bronze
FXLPDDR2A102HH0L_SIP 40nm LPDDR2-PHY command/address block for SIP Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > LPDDR3 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXLPDDR3AW101HH0L LPDDR3-PHY Command/address block for LightCo ; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Compensation > DDR2 - Compensation 
Cell Name Descriptions Type Process Gradation Literature
FXDDR2COMP010HE0A DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process Analog_IP 65nm Silver
FXDDR2COMP010HE0A DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process Analog_IP 65nm Silver
FXDDR2COMP010HF0A DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR2COMP010HF0A DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR2COMP011HC0H DDR2 PHY compensation block for 171 series (non BOAC); UMC 0.13um HS/FSG Logic Process Analog_IP 0.13um Silver
FXDDR2COMP012HC0H DDR2-PHY compensation block, BOAC; UMC 0.13um HS/FSG process Analog_IP 0.13um Silver
FXDDR2COMP012HC0H DDR2-PHY compensation block, BOAC; UMC 0.13um HS/FSG process Analog_IP 0.13um Silver
FXDDR2COMP013HD0A_FT
C
DDR2-PHY compensation block, BOAC; UMC 90nm SP/RVT Low-K Logic process Analog_IP 90nm Platinum
FXDDR2COMP013HD0A_FT
C
DDR2-PHY compensation block, BOAC; UMC 90nm SP/RVT Low-K Logic process Analog_IP 90nm Platinum
 
Interface Solution > DDR
> DDR PHY - Compensation > DDR3/3L - Compensation 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3COMP100HD0A DDR2/3 COMBO Compensation block (2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Porcess Analog_IP 90nm Silver
FXDDR3COMP100HH0L DDR23 COMBO PHY compensation Block ; UMC 40LP/RVT LowK Logic Process with 2.5V device Analog_IP 40nm Silver
FXDDR3COMP300HF0A Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3COMP300HF0A Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3COMP300HF0L Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Silver Minus
FXDDR3COMP400HF0A Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3COMP400HF0A Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3COMP400HF0A Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3COMP400HF0L Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Bronze
FXDDR3COMP502HJ0C Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process Analog_IP 28nm Contact Sales
FXDDR3COMP502NSHJ0C Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process; Vertical version Analog_IP 28nm Contact Sales
 
FXDDR3COMPFC502HH0L DDR3 Combo PHY Compensation Block for solder bump application; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
FXDDR3LTCOMP100HH0L compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process . Analog_IP 40nm Silver
FXDDR3LTCOMP100HH0L compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process . Analog_IP 40nm Silver
FXDDR3LTCOMP100HH0L compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process . Analog_IP 40nm Silver
FXDDR3LTCOMP100HH0L compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process . Analog_IP 40nm Silver
 
Interface Solution > DDR
> DDR PHY - Compensation > DDR4 - Compensation 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4COMP101HH0L UMC 40nm LP process DDR34/LPDDR23 COMPENSATION Block with 2.5V Device Analog_IP 40nm Contact Sales
 
Interface Solution > DDR
> DDR PHY - Compensation > LPDDR2 - Compensation 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3COMP50225EWHJ0
L
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 28nm HLP/RVT LowK Logic Process; Horizontal version Analog_IP 28nm Contact Sales
 
FXDDR3COMP50225NSHJ0
L
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 28nm HLP/RVT LowK Logic Process; Vertical version Analog_IP 28nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR1 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR1D173HF0A DDR1/MDDR PHY Data block ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process Analog_IP 55nm Bronze
 
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR2 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR2D172HR0B DDRII Data Block for Chip Application; UMC 0.11um HS/AE (AL Advance Enhancement) Logic Process Analog_IP 0.11um Bronze
 
FXDDR2D173HE0A DDR2/MDDR Combo PHY for Chip load usage ; UMC 65NM SP-RVT with 2.5V device LowK Logic Process Analog_IP 65nm Bronze
FXDDR2D173HF0A DDR2/MDDR COMBO PHY Data block for Chip usage ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process Analog_IP 55nm Silver
FXDDR2D174HE0A DDR2/MDDR PHY Data block ; UMC 65nm 1.0V with 2.5V device SP/RVT LowK Logic Process Analog_IP 65nm Silver
FXDDR2D174HF0A DDR2/MDDR Combo PHY data block ; UMC 55nm SP process with 2.5V device Analog_IP 55nm Silver
FXDDR2D200HC0H DDR2/MDDR Combo Data Block ; 0.13um Logic HS/FSG Logic Process Analog_IP 0.13um Bronze
FXDDR2D200HE0L DDR2/DDR1/MDDR Combo Data Block ; UMC 65nm LP/RVT LowK Logic Process Analog_IP 65nm Silver
FXDDR2D200HR0B Data block of 1:2 DDR2-PHY ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process Analog_IP 0.11um Silver Minus
FXDDR2D200HR0H 1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process Analog_IP 0.11um Silver
 
FXDDRIID171HC0H DDR2 PHY Data Block ;UMC 0.13um Logic HS/FSG Process Analog_IP 0.13um Gold
FXDDRIID172HC0H DDRII Data Block for Chip Application; UMC 0.13um HS/FSG Logic Process Analog_IP 0.13um Silver
FXDDRIID173HD0A_FTC DDR2-PHY data block with BOAC IO; UMC 90nm SP/RVT Lowk Logic Process Analog_IP 90nm Silver Minus
FXDDRIID174HD0A DDR2-PHY data block; UMC 90nm SP/RVT Lowk Process Analog_IP 90nm Gold
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR3 PHY - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3DIO502NSHJ0C_F
TC
IO Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR ; UMC 28nm HPC/RVT Logic Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR3/3L - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3D100HD0A DDR2/3 PHY Combo PHY data block (1.0v SP & 2.5V device); UMC 90nm SP/RVT LowK Logic Process Analog_IP 90nm Silver
FXDDR3D100HH0L DDR23 COMBO PHY Data Block ; UMC 40nm LP/RVT LowK Logic Process with 2.5V device Analog_IP 40nm Silver
FXDDR3D300HF0A Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3D300HF0A Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3D300HF0L Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Silver Minus
FXDDR3D402HF0A Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3D402HF0A Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3D403HF0A Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3D412HF0L Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Bronze
FXDDR3D502HF0A Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Contact Sales
 
FXDDR3D502HH0L Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process Analog_IP 40nm Silver Minus
FXDDR3DFC502HH0L DDR3 Combo PHY Data Block for solder bump application; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
FXDDR3LTD102HH0L DDR3/DDR3L/LPDDR2 combo PHY ( not support DDR3 leveling function), data block;UMC 40nm LP/RVT LowK Logic Process . Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR4 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4D16FC101HH0L 40nm LP DDR3/4 LPDDR23 COMBO PHY DATA Block for Flip Chip usage Analog_IP 40nm Contact Sales
 
FXDDR4DFD612HH0L Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process Analog_IP 40nm Contact Sales
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR4 PHY - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4D16FC602HH0L Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Data Block > LPDDR2 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXLPDDR2D102HH0L_SIP 40nm LPDDR2-PHY data block for SIP Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Data Block > LPDDR3 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4DFD612EWHJ0C Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 28nm Logic and Mixed-Mode Low-K HPC Process Analog_IP 28nm Contact Sales
 
FXDDR4DFD612NSHJ0C Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 28nm Logic and Mixed-Mode Low-K HPC Process Analog_IP 28nm Contact Sales
 
FXLPDDR3D16W101HH0L 40nm LPDDR3-PHY Data block for LightCo ; UMC 40nm LP/LVT Logic Process Analog_IP 40nm Contact Sales