Memory Compiler

Updated On:2018-04-25
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density & Low Power 1PRF, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSC0H_L_SY UMC 0.13-micron 1P8M 1.2V high speed (HS) logic process synchronous low power single port register file SRAM compiler Memory_IP 0.13um Platinum
FSF0A_L_SY UMC 55nm SP LowK Logic process low power synchronous high density one port register file compiler Memory_IP 55nm Silver
FSF0U_L_SY UMC 55nm ULP Logic Process Synchronous Low Power Feature RVT Periphery One-port Register File Compiler Memory_IP 55nm Contact Sales
 
FSH0L_H_SY UMC 40nm Low Power Process One Port Register File with 213 cell Memory_IP 40nm Silver Minus
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density & Low Power 1PRF, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_H_SYHVT UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with HVT peripheral. Memory_IP 40nm Silver Minus
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density & Low Power 1PRF, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_H_SYLVT UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with LVT peripheral. Memory_IP 40nm Silver Minus
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSD0A_B_SYHVT UMC 90nm Standard Performance LowK Logic Process Synchronous high density single port register file SRAM memory compiler Memory_IP 90nm Silver
FSF0G_L_SYHVT UMC 55nm ULP-SST process PG One Port Register File for periphery HVT Memory_IP 55nm Bronze
 
FSF0G_W_SYHVT 55ULP-SST 1P-RF with forward biased and HVT periphery Memory_IP 55nm Bronze
 
FSF0G_W_SYUHVT 55ULP-SST 1P-RF with forward biased and UHVT periphery Memory_IP 55nm Bronze
 
FSJ0P_D_SYHVT UMC 28HPC+ 1PRF compiler with HVT peripheral Memory_IP 28nm Contact Sales
 
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FS90A_C_SY UMC 0.25um Logic process standard synchronous single port register file SRAM memory compiler Memory_IP 0.25um Platinum
FSA0A_C_SY UMC 0.18um Logic GII process standard synchronous single port register file SRAM memory compiler. Memory_IP 0.18um Platinum
FSA0L_A_SY UMC 0.18um Logic LL process standard synchronous single port register file SRAM memory compiler. Memory_IP 0.18um Platinum
FSA0M_A_SY UMC 0.18UM Mixed Mode/RF; One Port Register File Memory Compiler Memory_IP 0.18um Contact Sales
 
FSB0G_A_SY UMC 0.15um SP Logic process standard synchronous single port register file SRAM memory compiler. Memory_IP 0.15um Silver
FSC0G_D_SY UMC 0.13um Logic SP (FSG) process high density synchronous single port register file SRAM memory compiler. Memory_IP 0.13um Silver
FSC0H_D_SY UMC 0.13um Logic HS (FSG) process synchronous single port register file SRAM memory compiler. Memory_IP 0.13um Platinum
FSC0I_A_SY UMC 0.13um 2P4M 1.5V CMOS image sensor process synchronous single port register file SRAM compiler. Memory_IP 0.13um Silver
FSC0L_D_SY UMC 0.13um Logic LL (FSG) process high density synchronous single port register file SRAM memory compiler. Memory_IP 0.13um Platinum
FSC0S_A_SY UMC 130nm CIS(CMOS Image Sensor)Cu process 1PRF compiler Memory_IP 0.13um Silver
FSC0U_D_SY UMC 0.13um HS/LL fusion (FSG) process high density synchronous single port register file SRAM memory compiler. Memory_IP 0.13um Gold
FSD0A_A_SY UMC 90nm Logic standard performance process synchronous high density single port register file SRAM memory compiler. Memory_IP 90nm Platinum
FSD0A_B_SY UMC 90nm 1P9M SP/RVT low_K logic process synchronous one port register file Memory_IP 90nm Platinum
FSD0K_A_SY UMC 90nm LL/RVT Synchronous high density single port register file SRAM memory compiler Memory_IP 90nm Silver
FSD0K_B_SY UMC 90nm Low Leakage Low-K RVT process synchronous one-port register file memory compiler Memory_IP 90nm Silver
FSE0A_A_SY UMC 65nm standard performance process synchronous high density single port register file SRAM memory compiler. Memory_IP 65nm Silver
FSE0A_B_SY UMC 65nm SP LowK Logic Process synchronous single port register file SRAM memory compiler. Memory_IP 65nm Contact Sales
 
FSE0K_A_SY UMC 65nm LL/RVt (Low K) Logic process synchronous single port SRAM Memory_IP 65nm Silver
FSF0A_A_SY UMC 55nm SP Low_K Logic process standard synchronous high density one port register file compiler. Memory_IP 55nm Silver
FSF0A_B_SY UMC 55nm Standard Performance LowK Logic Process synchronous single port register file SRAM using 0.425 bit cell Memory Compiler Memory_IP 55nm Silver
FSF0A_H_SY UMC 55nm SP/RVT LowK Logic Process standard synchronous Low Power (PG-DC) using 0.425 bit cell Single Port Register File memory compiler. Memory_IP 55nm Silver
FSF0F_A_SY UMC 55nm eFlash peocess One Port Register File memory compiler Memory_IP 55nm Bronze
FSF0L_A_SY UMC 55nm LP Logic Process 0.425um2 bit cell One Port Register File Memory Compiler Memory_IP 55nm Silver
FSH0L_B_SY UMC 40nm LP/HVT Logic Process with 6TSRAM (0.242 mm2) 1-port Register File Memory Compiler Memory_IP 40nm Silver
FSH0L_G_SQLVT UMC 40nm LP Logic Process Ultra High Speed One-Port Register File Memory_IP 40nm Silver
FSH0L_L_SY 40LP 1PRF with Sleep/retention/Nap mode feature Memory_IP 40nm Silver
FSJ0C_B_SY UMC 28nm HPC process One Port Register File Memory_IP 28nm Silver Minus
FSJ0C_D_SY UMC 28nm HPC Logic Process Ultra High Density 1-Port Register File Memory Compiler Memory_IP 28nm Silver Minus
FSJ0L_B_SY UMC 28nm HLP/Low-k One Port Register File Memory_IP 28nm Silver Minus
 
FSJ0P_D_SY UMC 28nm HPC Plus Process Standard Synchronous High Density Single Port Register File Memory Compiler. Memory_IP 28nm Contact Sales
 
FSL0A_C_SY UMC 0.153um Mixed-Mode/Logic process standard synchronous high density single port register file SRAM memory compiler Memory_IP 0.153um Silver
FSL0M_A_SY UMC 0.153um Logic/Mixed-Mode 3.3V MR process standard synchronous one port register file SRAM memory compiler. Memory_IP 0.153um Contact Sales
 
FSP0A_C_SY UMC 0.162um Logic GII process synchronous high density single port register file SRAM memory compiler Memory_IP 0.162um Silver
 
FSP0J_A_SY UMC 0.162um eFalsh/LL One Port Register File memory compiler Memory_IP 0.162um Bronze
FSR0B_B_SY UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process 1.41um2 cell One Port Register File Memory Compiler Memory_IP 0.11um Silver
FSR0B_D_SY UMC 0.11um HS/ALE Logic Process standard synchronous high density single port register file SRAM memory compiler. Memory_IP 0.11um Platinum
FSR0F_C_SY 110AE eFlash HS process for 1PRF compiler Memory_IP 0.11um Silver
FSR0H_B_SY UMC 0.11um HS/FSG Logic Process;One Port Register File Memory Compiler. Memory_IP 0.11um Silver
 
FSR0H_D_SY UMC 0.11um HS Logic process synchronous single port register file memory compiler Memory_IP 0.11um Platinum
FSR0I_A_SY UMC 0.11um CMOS Image Sensor 2P3M process standard synchronous high density single port register file SRAM memory compiler. Memory_IP 0.11um Bronze
FSR0K_B_SY UMC 0.11um LL/AE (AL Advanced Enhancement) Logic Process 1.41um2 cell Single Port Register File (1PRF) Memory Compiler Memory_IP 0.11um Silver
FSR0K_D_SY UMC 0.11um LL/ALE Logic Process standard asynchronous high density single port register file SRAM memory compiler. Memory_IP 0.11um Silver
FSR0L_D_SY UMC 0.11um LL/FSG process synchronous single port register file SRAM memory compiler. Memory_IP 0.11um Gold
FSR0P_A_SY 110AE eFlash LL process 1PRF Memory_IP 0.11um Silver
FSR0T_B_SY UMC 0.11um SP/AE Logic Process Synchronous One Port Register File Memory Compiler with 1.41um2 bit cell Memory_IP 0.11um Silver
FSR0T_D_SY UMC 0.11um SP/AE (AL Advance Enhancement) Logic Process standard synchronous high density single port register file SRAM memory compiler. Memory_IP 0.11um Silver
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM, Peri HVT, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSF0F_A_SYHVT UMC 55nm eFlash with peri HVT 1PRF Memory_IP 55nm Silver
FSF0F_L_SYHVT UMC 55nm eFlash One Port Register File with power-gating Memory_IP 55nm Silver
FSF0U_A_SYHVT UMC 55nm ULP Low-K process One Port Register File for periphery HVT Memory_IP 55nm Silver Minus
FSF0U_L_SYHVT UMC 55nm ULP process PG-One Port Register File for periphery HVT Memory_IP 55nm Silver Minus
FSF0U_W_SYHVT UMC 55nm uLP LowK Logic Process One Port Register File with well bias & periphery HVT Memory_IP 55nm Silver Minus
FSH0U_A_SYHVT UMC 40nm uLP Logic Process 1-Port Register File with Peri-HVT Memory_IP 40nm Contact Sales
 
FSJ0C_D_SYHVT UMC 28HPC 1PRF compiler with HVT peripheral Memory_IP 28nm Bronze
FSJ0C_L_SYHVT UMC 28nm HPC Logic process PG-One Port Register File with HVT Memory_IP 28nm Bronze
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM, Peri HVT/SVT 
Cell Name Descriptions Type Process Gradation Literature
FSN0U_D_SYHVT UMC 22uLP Logic Process 1-Port Register File Memory Compiler with HVT+SVT peripherals Memory_IP 22nm Contact Sales
 
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSF0G_A_SYHVT UMC 55nm Embedded Flash and Embedded E2PROM Ultra Low Power Split-Gate Process Memory_IP 55nm Bronze
FSH0L_B_SYLVT UMC 40nm LP Logic Process single port register file memory compiler with LVT periphery Memory_IP 40nm Silver
FSH0L_L_SYLVT 40LP 1PRF with Sleep/Retention/Nap mode & peri LVT feature Memory_IP 40nm Silver
FSJ0C_B_SYLVT UMC 28nm HPC process One Port Register File with LVT Memory_IP 28nm Bronze
 
FSJ0C_D_SYLVT UMC 28HPC process 1PRF compiler with LVT peripheral Memory_IP 28nm Bronze
FSJ0L_B_SYLVT UMC 28nm HLP Logic Process One Port Register File with LVT Memory_IP 28nm Bronze
 
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM, Peri LVT, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_L_SYLVT UMC 28nm HPC Logic process PG One Port Register File with LVT Memory_IP 28nm Bronze
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM, Peri uHVT 
Cell Name Descriptions Type Process Gradation Literature
FSF0U_W_SYUHVT UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery Memory_IP 55nm Silver Minus
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSF0F_L_SY UMC 55nm EFLASH Process ULL One Port Register File Memory_IP 55nm Bronze
FSF0L_L_SY UMC 55um LP Low-K process One Port Register File compiler Memory_IP 55nm Silver
FSJ0C_L_SY UMC 28nm HPC Logic process PG One Port Register File Memory_IP 28nm Silver Minus
 
Memory Compiler > 1-Port Register File
> 6TSRAM > Ultra High Speed 1PRF, 6TSRAM  
Cell Name Descriptions Type Process Gradation Literature
FSH0L_D_SY UMC 40nm Low Power Process One Port Register File wit 213 cell Memory_IP 40nm Silver Minus
FSJ0C_A_SQ UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler Memory_IP 28nm Bronze
FSJ0L_A_SQ UMC 28nm Logic process standard synchronous Ultra High Speed Single Port Register File SRAM memory compiler. Memory_IP 28nm Bronze
 
Memory Compiler > 1-Port Register File
> 6TSRAM > Ultra High Speed 1PRF, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_D_SYHVT UMC 40nm LP Logic Process one-port register file for area optimize with HVT peripheral Memory_IP 40nm Silver Minus
FSH0V_D_SYHVT UMC 40nm embedded high voltage (eHV) low power Process standard synchronous high density single port register file SRAM memory compiler. Memory_IP 40nm Bronze
 
Memory Compiler > 1-Port Register File
> 6TSRAM > Ultra High Speed 1PRF, 6TSRAM, Peri HVT/RVT 
Cell Name Descriptions Type Process Gradation Literature
FSN0U_A_SQHVT UMC 22nm uLP logic process Synchronous HVT+RVT Periphery Ultra-High-Speed One-Port Register File Compiler Memory_IP 22nm Contact Sales
 
FSN0U_L_SZHVT UMC 22uLP Logic process 2PRF memory compiler with NAP/RET/SLP mode Memory_IP 22nm Contact Sales
 
 
Memory Compiler > 1-Port Register File
> 6TSRAM > Ultra High Speed 1PRF, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_D_SYLVT UMC 40nm LP Logic Process one-port register file for area optimize with LVT peripheral Memory_IP 40nm Silver Minus
FSJ0C_A_SQLVT UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler with periphery LVT Memory_IP 28nm Silver Minus
FSJ0C_L_SELVT Synchronous LVT Periphery Ultra-High-Speed Single-Port SRAM Compiler Memory_IP 28nm Bronze
FSJ0L_A_SQLVT UMC 28nm HLP/UHS 1PRF compiler with peri LVT Memory_IP 28nm Bronze
 
Memory Compiler > 1-Port Register File
> 6TSRAM > Ultra High Speed 1PRF, 6TSRAM, Peri LVT/RVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0P_A_SQHVT UMC 28nm Logic and Mixed-Mode High Performance Process Synchronous HVT+RVT Periphery Ultra-High-Speed One-Port Register File Compiler Memory_IP 28nm Contact Sales
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > Asynchronous High Density 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FG70A_A_RS UMC 0.45um Logic process standard gate array asynchronous high density single port SRAM memory compiler. Memory_IP 0.45um Silver
FS70A_B_RH UMC 0.5um Logic process standard asynchronous high density single port SRAM memory compiler. Memory_IP 0.5um Platinum
FS80A_A_RH UMC 0.35um Logic process standard asynchronous high density single port SRAM memory compiler. Memory_IP 0.35um Platinum
FS80A_B_RH UMC 0.35um Logic process standard asynchronous high density single port SRAM memory compiler. Memory_IP 0.35um Platinum
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > Asynchronous Low Power 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FS70A_B_RA UMC 0.5um Logic process standard asynchronous low density low power single port SRAM memory compiler. Memory_IP 0.5um Platinum
FS80A_A_RA UMC 0.35um Logic process standard asynchronous low density low power single port SRAM memory compiler. Memory_IP 0.35um Platinum
FS80A_B_RA UMC 0.35um Logic process standard asynchronous low density low power single port SRAM memory compiler. Memory_IP 0.35um Platinum
FS90A_B_RA UMC 0.25um Logic process standard asynchronous low density low power single port SRAM memory compiler. Memory_IP 0.25um Platinum
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density & Low Power 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSF0F_L_SH UMC 55nm eFlash process process synchronous low power feature RVT peripheral high density single port SRAM compiler. Memory_IP 55nm Bronze
FSF0F_L_SHRED UMC 55nm eFlash process synchronous low power feature RVT peripheral high density single port SRAM compiler with row redundancy. Memory_IP 55nm Bronze
FSF0L_L_SH UMC 55um LP Low-K process ULL Singal-Port SRAM Compiler Memory_IP 55nm Silver
FSF0L_L_SHRED UMC 55um LP Low-K process Singal-Port SRAM Compiler with RED feature Memory_IP 55nm Silver
FSH0L_L_SH ULL Single Port SRAM ,UMC 40nm LP process. Memory_IP 40nm Silver
FSH0L_L_SHRED ULL Single Port SRAM with row redundancy , UMC 40nm LP Process. Memory_IP 40nm Silver Minus
FSH0U_B_SH UMC 40nm Low K Ultra Low Power Logic Process High-Density Single Port SRAM Compiler Memory_IP 40nm Contact Sales
FSJ0C_L_SH UMC 28nm HPC Logic Process PG Single Port SRAM memory compiler Memory_IP 28nm Silver Minus
FSJ0C_L_SHR1 UMC 28nm HPC process standard synchronous high density single port low power SRAM memory compiler with row redundancy Memory_IP 28nm Bronze
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density & Low Power 1PSRAM, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSF0F_L_SHHVT UMC 55nm eFlash Single-Port SRAM compiler with Power gating /HVT Memory_IP 55nm Silver
FSF0F_L_SHHVTRED UMC 55nm eFlash Single-Port SRAM with Row redundancy/HVT/Power -gating Memory_IP 55nm Silver
FSF0G_L_SHHVT UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler. Memory_IP 55nm Bronze
FSF0G_L_SHHVTRED UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler. Memory_IP 55nm Bronze
FSF0G_W_SHUHVT UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler. Memory_IP 55nm Bronze
FSF0U_L_SHHVT UMC 55nm ULP/LowK process Single-Port SRAM Memory_IP 55nm Silver Minus
FSF0U_L_SHHVTRED UMC 55nm ULP Low-K process, Single-Port SRAM with Row repair & periphery HVT Memory_IP 55nm Silver
 
FSH0L_L_SHHVT ULL Single Port SRAM with peri HVT, UMC 40nm LP process. Memory_IP 40nm Bronze
FSH0L_L_SHHVTRED ULL Sigle Port SRAM with HVT Row redundancy, UMC 40nm LP process. Memory_IP 40nm Silver Minus
FSH0L_L_SHLVT UMC 40nm LP/LVT SP-SRAM compiler with peri-LVT and Power gating Memory_IP 40nm Bronze
FSH0L_L_SHLVTRED UMC 40nm LP/LVT SP-SRAM compiler with power gating & row redundancy Memory_IP 40nm Bronze
FSJ0C_L_SHHVT UMC 28nm HPC Logic Process PG Single-Port SRAM with HVT memory compiler Memory_IP 28nm Bronze
FSJ0C_L_SHHVTR1 UMC 28nm HPC process standard synchronous HVT periphery high density single port low power SRAM memory compiler with row redundancy Memory_IP 28nm Bronze
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density & Low Power 1PSRAM, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_L_SHLVT UMC 28nm HPC Logic Process PG Single Port SRAM with LVT memory compiler Memory_IP 28nm Bronze
FSJ0C_L_SHLVTR1 UMC 28nm HPC process standard synchronous LVT periphery high density single port low power SRAM memory compiler with row redundancy Memory_IP 28nm Bronze
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density & Ultra Low Power 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSH0U_B_SHHVT UMC 40nm Low K Ultra Low Power Logic Process High-Density Single Port SRAM Compiler Memory_IP 40nm Contact Sales
FSH0U_B_SHRED UMC 40nm Low K Ultra Low Power Logic Process High-Density Single Port SRAM Compiler Memory_IP 40nm Contact Sales
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FS70A_B_SH UMC 0.5um Logic process standard synchronous high density single port SRAM memory compiler. Memory_IP 0.5um Platinum
FS80A_A_SH UMC 0.35um Logic process standard synchronous high density single port SRAM memory compiler. Memory_IP 0.35um Gold
FS80A_B_SH UMC 0.35um Logic process standard synchronous high density single port SRAM memory compiler. Memory_IP 0.35um Platinum
FS90A_B_SH UMC 0.25um Logic process standard synchronous high density single port SRAM memory compiler. Memory_IP 0.25um Platinum
FS90A_C_SH UMC 0.25um Logic process standard synchronous high density single port SRAM memory compiler. Memory_IP 0.25um Platinum
FSA0A_C_SU UMC 0.18um Logic GII process standard synchronous high speed single port SRAM memory compiler. Memory_IP 0.18um Platinum
FSA0A_D_SL UMC 0.18um Logic GII process synchronous High Density, Low Power mini single port SRAM Memory_IP 0.18um Platinum
FSA0F_A_SL UMC 0.18um e-flash GII process standard synchronous single port SRAM memory compiler. Memory_IP 0.18um Silver
FSA0F_B_SL UMC 0.18um eFlash process GII 4.0um2 Single Port SRAM Compiler Memory_IP 0.18um Silver
FSA0I_A_SL UMC 0.18um CIS process synchronous high density single port SRAM memory compiler. Memory_IP 0.18um Silver
FSA0L_A_SH UMC 0.18um Logic LL process standard synchronous high density single port SRAM memory compiler. Memory_IP 0.18um Silver
FSA0L_D_SL UMC 0.18um logic process high density, low power, mini area, single port SRAM compiler Memory_IP 0.18um Silver
FSA0M_A_SU UMC 0.18um mixed-mode process standard synchronous high density single port SRAM memory compiler. Memory_IP 0.18um Silver
FSA0V_A_SU UMC 0.18um high voltage 1.8V process synchronous high density single port SRAM memory compiler. Memory_IP 0.18um Silver
FSB0G_A_SH UMC 0.15um SP Logic process standard synchronous high density single port SRAM memory compiler. Memory_IP 0.15um Silver
FSC0G_D_SH UMC 0.13um Logic SP (FSG) process high density synchronous high density single port SRAM memory compiler. Memory_IP 0.13um Silver
FSC0H_D_SH UMC 0.13um Logic HS (FSG) process high density synchronous single port SRAM memory compiler. Memory_IP 0.13um Platinum
FSC0H_L_SH UMC 0.13um HS/FSG standard process synchronous high density low power single port SRAM memory compiler. Memory_IP 0.13um Platinum
FSC0I_A_SH UMC 0.13um CMOS image sensor process synchronous high density single port SRAM memory compiler. Memory_IP 0.13um Silver
FSC0L_D_SH UMC 0.13um Logic LL (FSG) process high density synchronous high density single port SRAM memory compiler. Memory_IP 0.13um Platinum
FSC0U_D_SH UMC 0.13um HS/LL fusion (FSG) process high density synchronous high density single port SRAM memory compiler. Memory_IP 0.13um Silver
FSD0A_A_SH UMC 90nm Logic process SP/low-k synchronous high density single port SRAM memory compiler Memory_IP 90nm Gold
FSD0A_A_SHRED UMC 90nm SP/Low-K Logic Process Synchronous High Density Single Port SRAM Compiler With Redundancy Memory_IP 90nm Silver
FSD0A_B_SH UMC 90nm SP/RVT Low-K Logic Process High Density Single Port 6T SRAM Memory Complier Memory_IP 90nm Platinum
FSD0A_B_SHRED UMC 90nm SP/RVT Low-K Logic Process Single Port SRAM (Introduce Redundancy feature to the existing FSD0A_B_SH) Memory_IP 90nm Silver
FSD0A_L_SH UMC 90nm SP Low-K Logic Process low power synchronous high density single port SRAM memory compiler. Memory_IP 90nm Bronze
FSD0I_A_SH UMC 90CIS 1P3M SP-SRAM compiler Memory_IP 90nm Silver Minus
FSD0I_A_SHRED 90CIS with Row redundancy SP-SRAM,UMC 90nm CIS Image Sensor Process. Memory_IP 90nm Bronze
FSD0K_A_SH UMC 90nm LL/RVT Synchronous high density one port SRAM memory compiler. Memory_IP 90nm Silver
FSD0K_A_SHRED UMC 90nm LL/RVT LowK Logic Process Synchronous High Density Single Port SRAM Compiler With Redundancy Memory_IP 90nm Silver
FSD0K_B_SH UMC 90nm LL Low-K RVT process synchronous single port SRAM memory compiler Memory_IP 90nm Silver
FSD0K_B_SHRED UMC 90nm LL/RVT Logic process standard synchronous high density single port SRAM memory compiler with redundancy feature. Memory_IP 90nm Silver
FSD0K_L_SH UMC 90nm Logic process low leakage devices synchronous Low-Power single port hihg density memory compiler. Memory_IP 90nm Silver
FSE0A_A_SH UMC 65nm SP LowK Logic Process standard synchronous high density single port SRAM memory compiler. Memory_IP 65nm Silver
FSE0A_A_SHRED UMC 65nm SP LowK Logic Process standard synchronous high density single port SRAM with redundaycy memory compiler. Memory_IP 65nm Silver
FSE0K_A_SH UMC 65nm LL/RVT LowK Logic Process 1-port high density memory compiler Memory_IP 65nm Silver
FSE0K_A_SHRED UMC 65nm LL/RVT LowK Process synchronous high density, single port SRAM compiler with the row redundancy. Memory_IP 65nm Silver
FSF0A_A_SH UMC 55nm SP Low_K Logic process standard synchronous high density single port SRAM memory compiler. Memory_IP 55nm Silver
FSF0A_A_SHRED UMC 55nm SP Low_K Logic process standard synchronous high density single port SRAM memory compiler with row-pair redundancy. Memory_IP 55nm Silver
FSF0A_B_SH UMC 55nm SP LowK Logic Process Synchronous One-Port SRAM using 0.425 bit cell Memory Compiler Memory_IP 55nm Silver
FSF0A_B_SHRED 55SP SPSRAM with row redundancy Memory_IP 55nm Silver
FSF0A_H_SH UMC 55nm SP/RVT LowK Logic Process standard synchronous Low Power (PG-DC) using 0.425 bit cell single port SRAM memory compiler. Memory_IP 55nm Silver
FSF0A_L_SH UMC 55nm SP LowK Logic Process low power synchronous high density single port SRAM memory compiler Memory_IP 55nm Silver
FSF0A_L_SHRED UMC 55nm SP LowK Logic Process low power synchronous high density single port SRAM memory compiler with redundancy Memory_IP 55nm Silver
FSF0A_N_SH UMC 55nm SP/RVT+HVT LowK Logic Process standard synchronous high density single port SRAM memory compiler. Memory_IP 55nm Silver
FSF0F_A_SH UMC 55nm eFlash Single-Port SRAM memory compiler Memory_IP 55nm Bronze
FSF0L_A_SH UMC 55nm LP LowK Logic Process Synchronous Single Port SRAM Memory Compiler Memory_IP 55nm Silver
FSF0L_A_SHRED UMC 55nm LP LowK Logic Process Synchronous SPRAM memory compiler with RED feature Memory_IP 55nm Silver
FSF0V_A_SH UMC 55nm eHV process;Single-Port SRAM compiler Memory_IP 55nm Silver Minus
FSF0V_A_SHRED UMC 55nm eHV process ; Single-Port SRAM compiler with Row redundancy Memory_IP 55nm Bronze
FSH0L_B_SH UMC 40nm LP/HVT Logic Process with 6TSRAM (0.242 mm2) One Port SRAM Memory Compiler Memory_IP 40nm Silver
FSH0L_B_SHRED UMC 40nm LP Logic Process Single Port SRAM memory compiler with row redundancy Memory_IP 40nm Silver
FSH0L_D_SH UMC 40nm Low Power Process SP-SRAM with 213 bit cell Memory_IP 40nm Silver Minus
FSH0L_D_SHRED UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell Memory_IP 40nm Bronze
FSH0L_H_SH UMC 40nm Low Power Process Single-Port SRAM 213cell with power gating Memory_IP 40nm Silver Minus
FSH0L_H_SHRED UMC 40nm Low Power Process PG SP-SRAM with Row redundancy for 213 bit cell Memory_IP 40nm Bronze
FSH0L_K_SH UMC 40nm Low Power Process Single-Port SRAM for dual power rail Memory_IP 40nm Bronze
FSH0L_L_SYHVT UMC 40nm LP with power gating & peri-HVT 1PRF Memory_IP 40nm Contact Sales
 
FSH0U_L_SYHVT UMC 40nm uLP process ULL One Port Register File memory compiler Memory_IP 40nm Bronze
FSJ0C_B_SH UMC 28nm Logic process standard synchronous RVT periphery high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0C_B_SHR1 UMC 28nm Logic process standard synchronous RVT periphery high density single port SRAM memory compiler with row redundancy. Memory_IP 28nm Bronze
FSJ0C_D_SH UMC 28nm HPC Logic Process Ultra High Density Single-Port SRAM Memory Compiler Memory_IP 28nm Silver Minus
FSJ0G_B_SH UMC 28nm HPM process standard synchronous high density single port SRAM memory compiler Memory_IP 28nm Silver Minus
FSJ0L_B_SH High Density Single Port SRAM, UMC 28nm HLP process Memory_IP 28nm Silver Minus
FSJ0L_B_SHC1 UMC 28nm HLP process standard synchronous high density single port SRAM memory compiler. Memory_IP 28nm Contact Sales
 
FSJ0L_B_SHR1 UMC 28nm HLP standard synchronous high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0L_B_SHR1C1 UMC 28nm HLP process standard synchronous High density single port SRAM memory compiler. Memory_IP 28nm Contact Sales
 
FSL0A_D_SL UMC 0.153um Mixed-Mode/Logic Process High Density, Low Power mini single port SRAM (porting of FSA0A_D_SL) Memory_IP 0.153um Silver
FSP0A_D_SL UMC 0.162um Logic GII process standard synchronous high density single port SRAM memory compiler. Memory_IP 0.162um Silver
 
FSP0J_A_SL UMC 0.162um eFalsh/LL Single-Port SRAM memory compiler Memory_IP 0.162um Bronze
FSR0A_A_SH 0.11um EE2PROM/LL 1.5v High density Single Port SRAM compiler Memory_IP 0.11um Silver Minus
FSR0B_B_SH UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process 1.41um2 Cell Single port SRAM compiler Memory_IP 0.11um Silver
FSR0B_D_SH UMC 0.11um HS/ALE logic process standard synchronous High-density single port SRAM memory compiler Memory_IP 0.11um Platinum
FSR0F_C_SH UMC 0.11um eFlash HS process ; Single-Port SRAM Memory Compiler Memory_IP 0.11um Silver
FSR0H_B_SH UMC 0.11um HS/FSG Logic Process;1.41um2 bit cell Single-Port SRAM Memory Compiler Memory_IP 0.11um Silver
FSR0H_D_SH UMC 0.11um HS Logic process synchronous, high density single port memory compiler Memory_IP 0.11um Gold
FSR0K_B_SH UMC 0.11um LL/AE (AL Advanced Enhancement) Logic Process Single Port SRAM compiler with 141 bit cell Memory_IP 0.11um Silver
FSR0K_D_SH UMC 0.11um LL/ALE Logic Process standard synchronous high density single port SRAM memory compiler. Memory_IP 0.11um Silver
FSR0L_D_SH UMC 0.11um Low Leakage Process Synchronous High Density Single-Port SRAM Compiler Memory_IP 0.11um Gold
FSR0P_A_SH 110AE eFlash LL SPSRAM Memory_IP 0.11um Silver
FSR0T_B_SH UMC 0.11um SP/AE Logic Process Synchronous Single-Port SRAM Memory compiler with 1.41um2 bit cell Memory_IP 0.11um Silver
FSR0T_D_SH UMC 0.11um SP/AE (AL Advance Enhancement) Logic Process standard synchronous High-density single port SRAM memory compiler. Memory_IP 0.11um Silver
FSR0U_A_SH UMC 0.11um Embedded High Voltage Mask Reduction AL Process standard synchronous high density single port SRAM memory compiler. Memory_IP 0.11um Bronze
FSR0V_A_SH UMC 0.11um HV Process 1.35um2 single port SRAM compiler Memory_IP 0.11um Silver
FSR0X_A_SH UMC 0.11um eFlash SP process; Single-Port SRAM compiler Memory_IP 0.11um Silver Minus
FST0J_A_SH UMC 80nm HV Process Single-Port SRAM Memory Compiler Memory_IP 80nm Silver
FST0J_A_SHRED UMC 80nm HV Process Single-Port SRAM Memory Compiler with Redundancy Memory_IP 80nm Silver
FST0J_L_SH UMC 80nm HV Process PG Single-Port SRAM Memory Compiler Memory_IP 80nm Silver Minus
FST0J_L_SHRED UMC 80nm HV Process Single-Port SRAM Memory Compiler with redundancy Memory_IP 80nm Bronze
FST0W_B_SH UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler. Memory_IP 80nm Silver Minus
FST0W_B_SHB4 UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler. Memory_IP 80nm Bronze
 
FST0W_B_SHRED UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler with redundancy. Memory_IP 80nm Silver Minus
FST0W_B_SHREDB4 UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler. Memory_IP 80nm Bronze
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM, Peri H/LVT 
Cell Name Descriptions Type Process Gradation Literature
FSF0V_B_SHHLVT UMC 55nm eHV Process Single Port SRAM Memory Compiler with Peripheral H/LVT using 277 bit-cell Memory_IP 55nm Silver Minus
FSF0V_B_SHHLVTRED UMC 55nm eHV Process Single Port SRAM with row redundancy for 277cell Memory_IP 55nm Bronze
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM, Peri H/RVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_D_SHHVTR1 UMC 28nm HPC Process Synchronous HVT/RVT Periphery High Density Single Port SRAM Memory Compiler with Row Redundancy Memory_IP 28nm Bronze
FSN0U_D_SHHRVT UMC 22nm ULP UHD SPSRAM compiler Memory_IP 22nm Contact Sales
 
FSN0U_D_SHHVT UMC 22nm ULP UHD SPSRAM compiler Memory_IP 22nm Contact Sales
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSF0F_A_SHHVT 55nm eFlash with Peri HVT SP-SRAM compiler Memory_IP 55nm Silver
FSF0F_A_SHHVTRED UMC 55nm eFlash with Peri HVT & RED SP-SRAM Memory_IP 55nm Silver
FSF0F_A_SHRED UMC 55nm EFLASH Processy Single-Port SRAM with row repair Memory complier Memory_IP 55nm Bronze
FSF0G_A_SHHVT UMC 55nm eflash/ulp process standard synchronous high density single port SRAM memory compiler. Memory_IP 55nm Bronze
FSF0G_A_SHHVTRED UMC 55nm SST/ulp Logic process standard synchronous high density single port SRAM memory compiler. Memory_IP 55nm Bronze
FSF0G_W_SHHVT UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler. Memory_IP 55nm Bronze
FSF0G_W_SHHVTRED UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler with row redundancy. Memory_IP 55nm Bronze
FSF0G_W_SHUHVTRED UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler with row redundancy. Memory_IP 55nm Bronze
FSF0I_A_SHHVT UMC 55nm CMOS Image Sensor 1P3M Process Single Port SRAM Memory Compiler with peri HVT Memory_IP 55nm Silver
FSF0I_A_SHHVTRED UMC 55nm CIS SP-SRAM with peri HVT and row redundancy Memory_IP 55nm Silver
FSF0U_A_SHHVT UMC 55nm ULP/LowK process Single-Port SRAM Memory_IP 55nm Silver Minus
 
FSF0U_A_SHHVTRED UMC 55nm ULP process , Single-Port SRAM with row repair and HVT Memory_IP 55nm Bronze
 
FSF0U_W_SHHVT UMC 55nm ULP/LowK Process Single-Port SRAM with well bias HVT Memory Compiler Memory_IP 55nm Silver Minus
FSF0U_W_SHHVTRED UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler Memory_IP 55nm Silver
FSF0U_W_SHUHVT UMC 55nm ULP/LowK Single-Port SRAM with Well Bias uHVT Memory_IP 55nm Silver Minus
FSF0U_W_SHUHVTRED UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler Memory_IP 55nm Bronze
FSF0V_A_SHHVT UMC 55EHV SP-SRAM compiler Memory_IP 55nm Silver
FSF0V_A_SHHVTRED UMC 55 EHV Process Single Port SRAM Memory Compiler with Row Redundancy Memory_IP 55nm Silver
FSH0L_D_SHHVT UMC 40nm LP Logic Process Single Port SRAM memory compiler using 213 bit -cell with peri-HVT Memory_IP 40nm Silver Minus
FSH0L_H_SHHVT UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-HVT Memory_IP 40nm Silver Minus
FSH0U_B_SHHVTRED UMC 40nm Low K Ultra Low Power Logic Process High-Density Single Port SRAM Compiler Memory_IP 40nm Contact Sales
FSH0U_L_SHHVT UMC 40nm uLP process ULL Single-Port SRAM Memory_IP 40nm Contact Sales
 
FSJ0C_D_SHHVT UMC 28nm HPC process synchronous HVT periphery high density single port SRAM memory compiler. Memory_IP 28nm Silver Minus
FSJ0P_D_SHHVT UMC 28HPC+ UHD SPSRAM compiler Memory_IP 28nm Contact Sales
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSF0V_A_SHLVT UMC 55nm HV SP-SRAM with peri LVT Memory_IP 55nm Silver
FSF0V_A_SHLVTRED UMC 55nm EHV Low Power Low-K process synchronous high density, single port SRAM compiler with row redundancy option. Memory_IP 55nm Silver
FSH0L_A_SEREDLVT UMC 40nm LP Logic Process Ultra High-Speed Single Port SRAM Memory compiler with Redundancy Memory_IP 40nm Silver Minus
FSH0L_B_SHLVT UMC 40nm LP Logic Process Single Port SRAM Compiler with LVT Periphery Memory_IP 40nm Silver
FSH0L_B_SHREDLVT UMC 40nm LP Logic Process Single Port SRAM Compiler LVT with row redundancy Memory_IP 40nm Silver
FSH0L_D_SHLVT UMC 40nm LP Logic Process Single Port SRAM Memory Compiler using 213 bit-cell with Peri-LVT Memory_IP 40nm Silver Minus
FSH0L_D_SHLVTRED UMC 40nm LP process synchronous high density (0.213LPHVT cell) single port SRAM compiler with row redundancy. Memory_IP 40nm Bronze
FSH0L_G_SELVT UMC 40um LP Logic Process High Speed Singl Port SRAM Compiler with 303RVT cell and Peri LVT Memory_IP 40nm Silver
FSH0L_H_SHLVT UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-LVT Memory_IP 40nm Silver Minus
FSH0L_H_SHLVTRED 40LP PG SP-SRAM LVT Peripheral with Row redundancy for 213 cell Memory_IP 40nm Bronze
FSJ0C_B_SHLVT UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler. Memory_IP 28nm Silver Minus
FSJ0C_B_SHLVTR1 UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0C_D_SHLVT UMC 28nm HPC process synchronous LVT periphery high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0C_D_SHLVTR1 UMC 28nm HPC Process Synchronous LVT/RVT Periphery High Density Single Port SRAM Memory Compiler with Row Redundancy Memory_IP 28nm Contact Sales
 
FSJ0L_B_SHLVT UMC 28nm HLP Logic process LVT standard synchronous high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0L_B_SHLVTC1 UMC 28nm HLP process standard LVT synchronous high density single port SRAM memory compiler. Memory_IP 28nm Contact Sales
 
FSJ0L_B_SHLVTR1 UMC 28nm HLP Logic process LVT standard synchronous high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0L_B_SHLVTR1C1 UMC 28nm HLP process LVT standard synchronous high density single port SRAM memory compiler. Memory_IP 28nm Contact Sales
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Speed 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FS70A_B_SU UMC 0.5um Logic process standard synchronous high density single port SRAM memory compiler. Memory_IP 0.5um Silver
FS80A_B_SU UMC 0.35um Logic process standard synchronous high speed single port SRAM memory compiler. Memory_IP 0.35um Platinum
FS90A_B_SU UMC 0.25um Logic process standard synchronous high speed single port SRAM memory compiler. Memory_IP 0.25um Platinum
FS90A_C_SU UMC 0.25um Logic process standard synchronous high speed single port SRAM memory compiler Memory_IP 0.25um Silver
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > Low Power 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FS80A_B_SA UMC 0.35um Logic process standard synchronous low density low power single port SRAM memory compiler. Memory_IP 0.35um Platinum
FS90A_B_SA UMC 0.25um Logic process standard synchronous low density low power single port SRAM memory compiler. Memory_IP 0.25um Platinum
FS90A_C_SA UMC 0.25um Logic Process standard synchronous single port Low Power SRAM memory compiler Memory_IP 0.25um Platinum
FS90A_C_SA UMC 0.25um Logic Process standard synchronous single port Low Power SRAM memory compiler Memory_IP 0.25um Platinum
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > Ultra High Density 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_D_SHR1 UMC 28nm HPC Logic Process Ultra High Density Single-Port SRAM Memory Compiler with Row Redundancy Memory_IP 28nm Contact Sales
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > Ultra High Speed 1PSRAM, 6T SRAM 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_A_SE UMC 28nm HPC Process Ultra High Speed Single-Port SRAM memory compiler Memory_IP 28nm Bronze
FSR0B_D_SE UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process Ultra High Speed Synchronous One Port SRAM Memory Compiler Memory_IP 0.11um Gold
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > Ultra High Speed 1PSRAM, 6T SRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_A_SELVT UMC 28nm HPC Process Ultra High Speed Single-Port SRAM Memory Compiler Memory_IP 28nm Silver Minus
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > Ultra High Speed 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSB0G_A_SE UMC 0.15um SP Logic process standard synchronousultra high speed single port SRAM memory compiler. Memory_IP 0.15um Silver
FSC0H_D_SE UMC 0.13um Logic HS (FSG) process synchronousultra high speed single port SRAM memory compiler. Memory_IP 0.13um Platinum
FSD0A_A_SE UMC 90nm SP-RVT/Low-k process synchronous ultra high speed SRAM compiler Memory_IP 90nm Platinum
FSD0T_A_SE UMC 90nm SPLVT ultra-high speed 1-port SRAM Memory_IP 90nm Contact Sales
 
FSE0A_A_SE UMC 65nm standard performance logic process synchronous extra high speed single port SRAM memory compiler. Memory_IP 65nm Silver Minus
FSF0A_A_SE UMC 55nm SP LowK Logic Process standard synchronous ultra high speed single port SRAM memory compiler. Memory_IP 55nm Silver
FSF0L_A_SE UMC 55nm Low-K/Low-Power Logic process synchronous ultra-high-speed single-port SRAM compiler. Memory_IP 55nm Bronze
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > Ultra High Speed 1PSRAM, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_A_SELVT UMC 40LP 303HVT cell /Peri-LVT Memory_IP 40nm Silver Minus
 
Memory Compiler > 2-Port Register File
> 6TSRAM > High Density and Ultra Low Power 2PRF, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSH0U_B_SV UMC 40nm logic Ultra Low Power Process Two Port Register File memory compiler(with 6T SRAM cell) Memory_IP 40nm Contact Sales
 
Memory Compiler > 2-Port Register File
> 6TSRAM > High Density and Ultra Low Power 2PRF, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0U_B_SVHVT UMC 40nm logic ultra low power process two port register file SRAM memory compiler(with 6T SRAM cell) Memory_IP 40nm Contact Sales
FSJ0P_L_SZHVT 28nm HPC+ logic process 2PRF with NAP/RET/SLP modes memory compiler Memory_IP 28nm Contact Sales
 
 
Memory Compiler > 2-Port Register File
> 8TSRAM > High Density & Low Power 2PRF, 8TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSC0H_L_SZ UMC 0.13um Logic HS FSG Synchronous high density low power two port register file SRAM memory compiler Memory_IP 0.13um Platinum
FSF0F_L_SZ UMC 55nm eflash process , Two Port Register File memory compiler Memory_IP 55nm Bronze
 
Memory Compiler > 2-Port Register File
> 8TSRAM > High Density 2PRF, 8TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FS90A_C_SZ UMC 0.25um Logic process standard synchronous two-port register file compiler. Memory_IP 0.25um Gold
 
FSA0A_C_SZ UMC 0.18um Logic GII process standard synchronous two port (1R1W) register file SRAM memory compiler. Memory_IP 0.18um Platinum
FSA0M_A_SZ UMC 0.18UM Mixed Mode/RF; Two Port Register File Memory_IP 0.18um Contact Sales
 
FSC0G_D_SZ UMC 0.13um Logic SP (FSG) process standard synchronous two port (1R1W) register file SRAM memory compiler. Memory_IP 0.13um Silver
FSC0H_D_SZ UMC 0.13um logic HS(FSG) Process Synchronous two port register file SRAM memory compiler. Memory_IP 0.13um Platinum
FSC0L_D_SZ UMC 0.13um Logic LL (FSG) process high density synchronous two port register file SRAM memory compiler. Memory_IP 0.13um Platinum
FSC0U_D_SZ UMC 0.13um HS/LL fusion (FSG) process high density synchronous two port register file SRAM memory compiler. Memory_IP 0.13um Gold
FSD0A_A_SZ UMC 90nm Logic SP (LowK) process standard synchronous two port (1R1W) register file SRAM memory compiler. Memory_IP 90nm Platinum
FSD0K_A_SZ UMC 90nm LL/RVT Synchronous high density two-port register file memory compiler Memory_IP 90nm Silver
FSE0A_A_SZ UMC 0.65um SP/RVT LowK logic process synchronous two-port register file memory compiler Memory_IP 65nm Silver
FSE0K_A_SZ UMC 65nm LL/RVT (Low K) logic process standard synchronous high density two port register file SRAM memory compiler. Memory_IP 65nm Silver
FSF0A_A_SZ UMC 55nm SP LowK Logic Process standard synchronous two port register file memory compiler. Memory_IP 55nm Silver
FSF0A_L_SZ UMC 55nm Standard Performance LowK Logic Process Two-Port Register File Memory_IP 55nm Contact Sales
 
FSF0F_A_SZ UMC 55nm EFLASH Process Two Port Register File Memory_IP 55nm Bronze
FSF0L_A_SZ UMC 55nm LP Logic Process Synchronous 2-Port Register File Memory Compiler Memory_IP 55nm Silver
FSF0L_L_SZ UMC 55nm LP/Low-K process PG Two Port Register File compiler. Memory_IP 55nm Silver Minus
FSH0L_A_SZ UMC 40nm LP/RVT LowK Logic 2-Port Register File Memory Compiler Memory_IP 40nm Silver
FSH0L_B_SZ UMC 40nm LP/Low-K process ; Two Port Register File memory compiler Memory_IP 40nm Silver
FSH0L_L_SZ 40LP 2PRF with Sleep/Retention/Nap mode feature Memory_IP 40nm Silver Minus
FSJ0C_A_SZ UMC 28nm HPC process Two Port Register File Memory_IP 28nm Silver Minus
FSJ0C_A_SZB2 UMC 28nm HPC process 2PRF with Bank2 Memory_IP 28nm Contact Sales
 
FSJ0C_A_SZB4 UMC 28nm HPC process Two Port Register File with Bank2 Memory_IP 28nm Bronze
FSJ0L_A_SZ UMC 28nm HLP/Low-K 2PRF compiler Memory_IP 28nm Silver Minus
FSL0A_C_SZ UMC 0.153um Mixed-Mode/Logic process standard synchronous two port (1R1W) register file SRAM memory compiler Memory_IP 0.153um Silver
FSP0A_C_SZ UMC 0.162um Logic process standard synchronous two port register file SRAM memory compiler. Memory_IP 0.162um Silver
 
FSR0B_D_SZ UMC 0.11um HS/ALE Logic Process synchronous two port register file memory compiler Memory_IP 0.11um Platinum
 
FSR0F_C_SZ UMC 0.11um eFlash HS process; Two Port Register File Memory_IP 0.11um Silver
FSR0H_B_SZ UMC 0.11um HS/FSG Logic Process Synchronous 2PRF with 339cell Memory Compiler Memory_IP 0.11um Silver
FSR0H_D_SZ UMC 0.11um HS Logic process standard synchronous two port register file SRAM memory compiler Memory_IP 0.11um Platinum
FSR0K_D_SZ UMC 0.11um LL/ALE Logic process standard synchronous high density two port register file SRAM memory compiler. Memory_IP 0.11um Silver
FSR0L_D_SZ UMC 0.11um Logic(LL) FSG process synchronous two port register file memory compiler Memory_IP 0.11um Gold
FSR0P_A_SZ 110AE eFlsh LL process 2 Port RF Memory_IP 0.11um Silver
FSR0T_D_SZ UMC 0.11um SP/AE (AL Advance Enhancement) Logic Process synchronous two port SRAM memory compiler. Memory_IP 0.11um Silver
 
Memory Compiler > 2-Port Register File
> 8TSRAM > High Density 2PRF, 8TSRAM, Dual Power Rail 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_T_SZ UMC 40nm Low Power Process , Two Port Register File with dual power rail Memory_IP 40nm Contact Sales
 
Memory Compiler > 2-Port Register File
> 8TSRAM > High Density 2PRF, 8TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSD0A_A_SZHVT UMC 90nm Standard Performance Lowk Process Two Port SRAM Register File Compiler. Memory_IP 90nm Silver
FSH0L_L_SZHVT UMC 40nm Logic process standard Synchronous High Density Two Port Register File SRAM memory compiler. Memory_IP 40nm Contact Sales
 
Memory Compiler > 2-Port Register File
> 8TSRAM > High Density 2PRF, 8TSRAM, Peri HVT, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_L_SZHVT UMC 28nm HPC process PG Two Port Register File with peri-HVT Memory_IP 28nm Bronze
FSJ0C_L_SZHVTB2 UMC 28nm HPC process 2PRF, HVT & Bank2 Memory_IP 28nm Bronze
FSJ0C_L_SZHVTB4 UMC 28nm HPC process PG-2PRF with HVT Bank4 Memory_IP 28nm Bronze
 
Memory Compiler > 2-Port Register File
> 8TSRAM > High Density 2PRF, 8TSRAM, Peri HVT/SVT 
Cell Name Descriptions Type Process Gradation Literature
FSN0U_A_SJHVT UMC 22uLP Logic Process dual-Port Register File Memory Compiler with HVT+SVT peripheral Memory_IP 22nm Contact Sales
 
 
Memory Compiler > 2-Port Register File
> 8TSRAM > High Density 2PRF, 8TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_A_SZLVT UMC 40nm LP Logic Process Two-Port Register File with LVT Peripheral Memory Compiler Memory_IP 40nm Contact Sales
 
FSH0L_B_SZLVT UMC 40nm LP/LVT Process; Two Port Register File with LVT Memory_IP 40nm Silver
FSH0L_L_SZLVT 40LP 2PRF with Sleep/Retention/Nap mode & peri LVT feature Memory_IP 40nm Silver Minus
FSJ0C_A_SZLVT UMC 28nm HPC process Two Port Register File with peri LVT Memory_IP 28nm Silver Minus
FSJ0C_A_SZLVTB2 UMC 28nm HPC process Two Port Register File with LVT and Bank2 Memory_IP 28nm Bronze
FSJ0C_A_SZLVTB4 UMC 28nm HPC process Two Port Register File with LVT and Bank4 Memory_IP 28nm Bronze
FSJ0L_A_SZLVT 28HLP periphery LVT Two Port Register File Memory Compiler Memory_IP 28nm Bronze
 
Memory Compiler > 2-Port Register File
> 8TSRAM > High Density 2PRF, 8TSRAM, Peri LVT, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_L_SZLVT UMC 28nm HPC process PG Two Port Register File with peri-LVT Memory_IP 28nm Bronze
FSJ0C_L_SZLVTB2 UMC 28nm HPC process 2PRF with LVT and Bank 2 Memory_IP 28nm Bronze
FSJ0C_L_SZLVTB4 UMC 28nm HPC process PG-2PRF with LVT and Bank 2 Memory_IP 28nm Bronze
 
Memory Compiler > 2-Port Register File
> 8TSRAM > High Density 2PRF, 8TSRAM, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_L_SZ UMC 28nm HPC process PG Two Port Register File Memory_IP 28nm Silver Minus
FSJ0C_L_SZB2 UMC 28nm HPC process 2PRF with Bank2 & power gating Memory_IP 28nm Bronze
 
FSJ0C_L_SZB4 UMC 28nm HPC process PG-2PRF with Bank4 Memory_IP 28nm Bronze
 
Memory Compiler > 2-Port Register File
> 8TSRAM > Ultra High Density 2PRF, 8TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSF0A_A_SV UMC 55nm SP-RVT and HVT LowK Logic Process standard synchronous ultra high density/6T cell two port register file memory compiler. Memory_IP 55nm Silver
 
Memory Compiler > 2-Port SRAM
> 8TSRAM > Asynchronous High Density 2PSRAM, 8TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FG70A_A_RG UMC 0.45um Logic process standard gate array asynchronous embedded array high density two port (1R1W) SRAM memory compiler. Memory_IP 0.45um Silver
FS70A_B_RB UMC 0.5um Logic process standard asynchronous high density two port (1R1W) SRAM memory compiler. Memory_IP 0.5um Gold
FS80A_A_RB UMC 0.35um Logic process standard asynchronous high density two port (1R1W) SRAM memory compiler. Memory_IP 0.35um Gold
FS80A_B_RB UMC 0.35um Logic process standard asynchronous high density two port (1R1W) SRAM memory compiler. Memory_IP 0.35um Gold
 
Memory Compiler > 2-Port SRAM
> 8TSRAM > Asynchronous Low Power 2PSRAM, 8TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FS70A_B_RW UMC 0.5um Logic process standard asynchronous low density low power two port (1R1W) SRAM memory compiler. Memory_IP 0.5um Gold
FS80A_A_RW UMC 0.35um Logic process standard asynchronous low density low power two port (1R1W) SRAM memory compiler. Memory_IP 0.35um Platinum
FS80A_B_RW UMC 0.35um Logic process standard asynchronous low density low power two port (1R1W) SRAM memory compiler. Memory_IP 0.35um Platinum
 
Memory Compiler > 2-Port SRAM
> 8TSRAM > High Density 2PSRAM, 8TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FS80A_A_SB UMC 0.35um Logic process standard synchronous high density two port (1R1W) SRAM memory compiler. Memory_IP 0.35um Gold
FS80A_B_SB UMC 0.35um Logic process standard synchronous high density two port (1R1W) SRAM memory compiler. Memory_IP 0.35um Gold
 
Memory Compiler > 2-Port SRAM
> 8TSRAM > Low Power 2PSRAM, 8TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FS80A_A_SW UMC 0.35um Logic process standard synchronous low density low power two port (1R1W) SRAM memory compiler. Memory_IP 0.35um Gold
FS80A_B_SW UMC 0.35um Logic process standard synchronous low density low power two port (1R1W) SRAM memory compiler. Memory_IP 0.35um Platinum
FS90A_B_SW UMC 0.25um Logic process standard synchronous low density low power two port (1R1W) SRAM memory compiler. Memory_IP 0.25um Platinum
 
Memory Compiler > 2-Port SRAM
> 8TSRAM > Synchronous High Density 2PSRAM, 8TSRAM peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_A_SZHVTB4 UMC 28HPC Process Standard Synchronous High Density Two Port SRAM Memory Compiler. Memory_IP 28nm Bronze
 
Memory Compiler > Dual-Port SRAM
> 6TSRAM > High Density DPSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSA0F_C_SJ UMC 0.18um eFlash GII process High density dual port SRAM compiler Memory_IP 0.18um Silver
 
Memory Compiler > Dual-Port SRAM
> 6TSRAM > High Density DPSRAM, 6TSRAM, Peri LVT, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_L_SJLVT UMC 28nm HPC process PG-Dual Port SRAM with LVT Memory_IP 28nm Bronze
FSJ0C_L_SJLVTR1 UMC 28nm HPC process PG Dual Port SRAM with LVT Memory_IP 28nm Bronze
 
 
Memory Compiler > Dual-Port SRAM
> 6TSRAM > High Density DPSRAM, 6TSRAM, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_L_SJ UMC 28nm HPC process Dual Port SRAM with Power gating Memory_IP 28nm Bronze
FSJ0C_L_SJR1 UMC 28nm HPC Process dual port SRAM with power gating Memory_IP 28nm Bronze
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSA0A_B_SJ UMC 0.18um Logic GII process standard synchronous high density dual port (2RW) SRAM memory compiler. Memory_IP 0.18um Gold
FSA0A_C_SJ UMC 0.18um Logic GII process standard synchronous high density dual port (2RW) SRAM memory compiler. Memory_IP 0.18um Platinum
FSA0M_A_SJ UMC 0.18um MM/RF process standard synchronous high density dual port SRAM memory compiler Memory_IP 0.18um Silver
FSC0C_A_SJ UMC 0.13um Al Standard performance process standard synchronous high density dual port SRAM compiler Memory_IP 0.13um Contact Sales
 
FSC0G_D_SJ UMC 0.13um Logic SP (FSG) process high density synchronous high density dual port (2RW) SRAM memory compiler. Memory_IP 0.13um Silver
FSC0H_D_SJ UMC 0.13um Logic HS (FSG) process high density synchronous dual port (2RW) SRAM memory compiler. Memory_IP 0.13um Platinum
FSC0H_D_SJBTI UMC 0.13um HS/FSG Logic process Synchronous high density dual port SRAM memory compiler with input wrapper mux Memory_IP 0.13um Gold
FSC0L_D_SJ UMC 0.13um Logic LL (FSG) process high density synchronous high density dual port (2RW) SRAM memory compiler. Memory_IP 0.13um Platinum
FSC0U_D_SJ UMC 0.13um HS/LL fusion (FSG) process high density synchronous high density dual port (2RW) SRAM memory compiler. Memory_IP 0.13um Silver
FSD0A_A_SJ UMC 90nm SP-RVT/Low-k process synchronous dual-port SRAM compiler Memory_IP 90nm Platinum
FSD0K_A_SJ UMC 90nm LL/RVT Synchronous high density dual-port SRAM memory compiler Memory_IP 90nm Silver
FSD0K_L_SJ UMC 90nm LL/RVT Low-k Logic Process Synchronouslow AC power dual-port SRAM Memory_IP 90nm Bronze
FSE0A_A_SJ UMC 65nm 1P10M 1.0v SP LowK Logic Process synchronous high density dual-port SRAM compiler (with row redundancy option) Memory_IP 65nm Silver
FSE0A_A_SJRED UMC 65nm logic SP-RVT and HVT (Lowk) Process synchronous, high density, dual-port SRAM compiler with the row redundancy option Memory_IP 65nm Silver Minus
FSE0K_A_SJ UMC 65nm Low Leakage RVT Logic Low_K process standard synchronous high density dual port SRAM memory compiler. Memory_IP 65nm Silver
FSE0K_A_SJBTI UMC 65nm Low Leakage RVT Logic Low_K process standard synchronous high density dual port SRAM memory compiler with bist testing interface. Memory_IP 65nm Silver
 
FSE0K_A_SJRED UMC 65nm Low Leakage RVT Logic Low_K process standard synchronous high density dual port SRAM memory compiler wiht redundancy elements. Memory_IP 65nm Silver
FSE0K_A_SJREDBTI UMC 65nm Low Leakage RVT Logic Low_K process standard synchronous high density dual port SRAM memory compiler with redundancy elements and bist testing interface. Memory_IP 65nm Silver
 
FSF0A_A_SJ UMC 55nm SP LowK Logic Process standard synchronous dual-port RAM memory compiler. Memory_IP 55nm Silver
FSF0A_A_SJRED UMC 55nm 1P10M 1.0V Standard Performance (SP) Lowk Logic Process synchronous, high density, dual-port SRAM with row redundancy option Memory_IP 55nm Silver
FSF0A_L_SJ UMC 55nm SP LowK Logic Process low power synchronous high density dual port SRAM memory compiler. Memory_IP 55nm Silver
FSF0A_L_SJRED UMC 55nm SP LowK Logic Process low power synchronous high density dual port SRAM memory compiler with redundancy. Memory_IP 55nm Silver
FSF0A_O_SJ 55 SP Dual Port SRAM compiler with 1P4M metal option Memory_IP 55nm Bronze
FSF0F_A_SJ UMC 55nm EFLASH Process Dual-Port SRAM Memory Compiler Memory_IP 55nm Bronze
FSF0F_A_SJRED UMC 55nm eFlash Process Dual-Port SRAM with Row redundancy Memory_IP 55nm Bronze
FSF0F_L_SJ UMC 55nm eFlash eFlash Dual-Port SRAM Memory Compiler Memory_IP 55nm Bronze
FSF0F_L_SJRED 55nm eFlash Dual-Port SRAM memory compiler with row redundancy Memory_IP 55nm Bronze
FSF0L_A_SJ UMC 55nm LP Logic Process Synchronous Dual-Port SRAM Memory Compiler Memory_IP 55nm Silver
FSF0L_A_SJRED UMC 55nm LP Logic Process Synchronous Dual-Port SRAM with RED feature Memory_IP 55nm Silver
FSF0L_L_SJ UMC 55nm LP process with PG Dual port SRAM compiler Memory_IP 55nm Contact Sales
 
FSF0L_L_SJRED UMC 55nm LP/Low-K Process with Row Redundancy Dual Port SRAM compiler Memory_IP 55nm Silver Minus
FSH0L_A_SJ UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler. Memory_IP 40nm Silver
FSH0L_A_SJRED UMC 40nm Logic Process standard synchronous high density dual port SRAM memory compiler with redundancy Memory_IP 40nm Silver
FSH0L_C_SJ 40LP High density dual port SRAM compiler with Vss booster feature Memory_IP 40nm Silver Minus
FSH0L_C_SJRED UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy Memory_IP 40nm Silver Minus
FSH0L_T_SJ UMC 40nm Low Power Process Dual-Port SRAM compiler with dual power rail Memory_IP 40nm Bronze
FSJ0C_A_SJ UMC 28nm HPC process Dual Port SRAM compiler Memory_IP 28nm Bronze
FSJ0C_A_SJR1 UMC 28nm HPC process Dual Port SRAM with row reapir Memory_IP 28nm Bronze
FSJ0C_L_SJHVT UMC 28nm HPC process standard synchronous high density dual port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0L_A_SJ UMC 28nm HLP/Low-k Dual-Port SRAM compiler Memory_IP 28nm Contact Sales
 
FSJ0L_A_SJR1 UMC 28nm HLP Logic Process ; Dual Port SRAM compiler with R1 Memory_IP 28nm Contact Sales
 
FSL0A_C_SJ UMC 153nm Mixed-Mode/Logic process standard synchronous high density dual port SRAM memory compiler. Memory_IP 0.153um Silver
FSR0B_D_SJ UMC 0.11um HS/ALE Logic Process standard synchronous High-density dual port SRAM memory compiler Memory_IP 0.11um Silver
FSR0F_C_SJ UMC 0.11um eFlash HS process; Dual Port SRAM compiler Memory_IP 0.11um Silver
FSR0H_D_SJ UMC 0.11um HS/RVT Logic process standard synchronous high density dual port SRAM memory compiler. Memory_IP 0.11um Silver
FSR0K_D_SJ UMC 0.11um LL/ALE (AL Enhancement) Logic Process standard synchronous high density dual port SRAM memory compiler. Memory_IP 0.11um Silver
FSR0L_D_SJ UMC 0.11um Low Leakage Logic process standard synchronous high density dual port SRAM memory compiler. Memory_IP 0.11um Gold
FSR0P_A_SJ UMC 0.11um eFlash LL process Dual port SRAM compiler Memory_IP 0.11um Bronze
 
FSR0T_D_SJ UMC 0.11um SP/AE (AL Advance Enhancement) Logic Process standard synchronous High-density dual port SRAM memory compiler. Memory_IP 0.11um Gold
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSF0V_A_SJHVT UMC 55nm EHV Dual Port SRAM Compiler with peri-HVT Memory_IP 55nm Silver Minus
FSF0V_A_SJHVTRED UMC 55nm EHV Dual Port SRAM compiler with peri_HVT Memory_IP 55nm Bronze
FSJ0C_A_SJHVT UMC 28nm HPC process Dual Port SRAM compiler Memory_IP 28nm Bronze
FSJ0C_A_SJHVTR1 UMC 28nm HPC process Dual Port SRAM compiler Memory_IP 28nm Bronze
FSJ0C_L_SJHVTR1 UMC 28HPC process standard synchronous high density dual port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0P_A_SJHVT UMC 28nm HPC+ process dual port SRAM memory compiler with HVT+RVT peripheral Memory_IP 28nm Contact Sales
 
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM, Peri HVT, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_L_SJHVTRED UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler Memory_IP 40nm Contact Sales
 
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_A_SJLVT UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with LVT Memory_IP 40nm Silver
FSH0L_A_SJREDLVT UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with ROW redundancy with LVt peripheral Memory_IP 40nm Silver
FSH0L_C_SJLVT UMC 40nm LP Logic Process Dual-Port SRAM Memory Compiler with LVT peripheral Memory_IP 40nm Silver Minus
FSH0L_C_SJLVTRED UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral Memory_IP 40nm Silver Minus
FSJ0C_A_SJLVT UMC 28nm HPC process Dual Port SRAM with LVT Memory_IP 28nm Bronze
FSJ0C_A_SJLVTR1 UMC 28nm HPC process Dual Port SRAM with row repair & LVT Memory_IP 28nm Bronze
FSJ0L_A_SJLVT UMC 28nm HLP Logic Process ; Dual Port SRAM compiler with LVT Memory_IP 28nm Contact Sales
 
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM, Peri LVT, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_L_SJLVT UMC 40nm LP LowK Logic Process ULL Dual-Port SRAM Memory Compiler with Peri-LVT Memory_IP 40nm Silver Minus
FSH0L_L_SJLVTRED UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler Memory_IP 40nm Bronze
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_L_SJ UMC 40nm LP Dual Port SRAM compiler with Sleep/Retention mode Memory_IP 40nm Silver Minus
FSH0L_L_SJRED UMC 40nm Low-K Low Power synchronous Feature Dual Port SRAM memory compiler Memory_IP 40nm Silver Minus
 
Memory Compiler > ROM
> Contact ROM > Contact ROM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSF0G_A_SPHVT UMC 55nm Logic process standard synchronous Contact ROM memory compiler. Memory_IP 55nm Bronze
 
FSF0G_L_SPHVT UMC 55nm Logic process standard synchronous Contact ROM memory compiler. Memory_IP 55nm Bronze
 
Memory Compiler > ROM
> Contact ROM > Contact ROM, Peri RVT/HVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_B_SPHVT UMC 28HPC RVT/HVT Logic Process Standard Synchronous Contact ROM memory Compiler. Memory_IP 28nm Bronze
 
 
Memory Compiler > ROM
> Contact ROM > Contact ROM, Peri RVT/LVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_B_SPLVT UMC 28HPC LVT/RVT Logic Process Standard Synchronous Contact ROM memory Compiler. Memory_IP 28nm Bronze
 
Memory Compiler > ROM
> Diffusion ROM > Diffusion ROM 
Cell Name Descriptions Type Process Gradation Literature
FS70A_B_SD UMC 0.5um Logic process standard synchronous diffusion programmed ROM memory compiler. Memory_IP 0.5um Platinum
FS80A_B_SD UMC 0.35um Logic process standard synchronous diffusion programmed ROM memory compiler. Memory_IP 0.35um Platinum
FS90A_B_SD UMC 0.25um Logic process standard synchronous diffusion programmed ROM memory compiler. Memory_IP 0.25um Platinum
FS90A_B_SI UMC 0.25um Logic process standard synchronous high speed diffusion programmed ROM memory compiler. Memory_IP 0.25um Gold
FS90A_C_SI UMC 0.25um Logic process standard synchronous Diffusion ROM memory compiler. Memory_IP 0.25um Gold
FSA0L_A_SD UMC 0.18um Logic Low Leakage process synchronous Diffusion ROM complier Memory_IP 0.18um Silver
FSP0A_C_SD UMC 0.162um Logic Process standard synchronous diffusion programmable ROM memory compiler. Memory_IP 0.162um Silver
 
 
Memory Compiler > ROM
> Metal ROM > Metal ROM 
Cell Name Descriptions Type Process Gradation Literature
FG70A_A_RM UMC 0.45um Logic process standard gate array asynchronous metal programmed ROM memory compiler. Memory_IP 0.45um Gold
FSC0U_D_SM UMC 0.13um Fusion Logic process standard synchronous Metal-1 ROM memory compiler. Memory_IP 0.13um Silver
FSP0V_A_SM UMC 0.162um EHV process standard synchronous 1P2M Metal ROM memory compiler. Memory_IP 0.162um Silver
 
 
Memory Compiler > ROM
> Pcode ROM 
Cell Name Descriptions Type Process Gradation Literature
FSR0A_A_SK UMC 0.11um EE2PROM/LL Process PCode ROM Compiler Memory_IP 0.11um Silver Minus
FSR0E_A_SK UMC 0.11um EE2PROM AE LL Process Pcode ROM Memory_IP 0.11um Bronze
 
Memory Compiler > ROM
> Pcode ROM > Pcode ROM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSF0F_A_SKHVT UMC 55nm eFlash process with peri-HVT Pcode ROM compiler Memory_IP 55nm Silver Minus
 
Memory Compiler > ROM
> VIA ROM 
Cell Name Descriptions Type Process Gradation Literature
FSC0S_A_SP UMC 0.13um CIS(CMOS Image Sensor)Cu process ROM compiler Memory_IP 0.13um Silver
FSF0F_L_SP UMC 55nm eFlash process process ULL ROM Memory Compiler Memory_IP 55nm Bronze
FSF0U_L_SP UMC 55nm low k ultral low power VIA1 programmable ROM compiler Memory_IP 55nm Contact Sales
 
FSN0U_A_SPHVT UMC 22nm uLP logic process via1 rom complier Memory_IP 22nm Contact Sales
 
 
Memory Compiler > ROM
> VIA ROM > VIA ROM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSF0U_L_SPHVT UMC 55nm ULP process ROM compiler with HVT peripheral Memory_IP 55nm Silver Minus
 
Memory Compiler > ROM
> VIA1 ROM > VIA1 ROM 
Cell Name Descriptions Type Process Gradation Literature
FS90A_C_SP UMC 0.25um process standard Synchronous VIA1 programmable ROM Compiler. Memory_IP 0.25um Silver
FS90A_C_SP UMC 0.25um process standard Synchronous VIA1 programmable ROM Compiler. Memory_IP 0.25um Silver
FSA0A_B_SP UMC 0.18um Logic GII process standard synchronous VIA1 programmed ROM memory compiler. Memory_IP 0.18um Platinum
FSA0A_C_SP UMC 0.18um Logic GII process standard synchronous VIA1 programmed ROM memory compiler. Memory_IP 0.18um Platinum
FSA0A_D_SP UMC 0.18um Logic GII process synchronous VIA1 ROM memory compiler. Memory_IP 0.18um Platinum
FSA0L_A_SP UMC 0.18um Logic LL process standard synchronous VIA1 programmed ROM memory compiler. Memory_IP 0.18um Platinum
FSA0L_D_SP UMC 0.18um Low Leakage(LL) Logic process standard synchronous Via1 ROM memory compiler. Memory_IP 0.18um Silver
FSC0G_D_SP UMC 0.13um Logic SP (FSG) process high density synchronous Via-1 ROM memory compiler Memory_IP 0.13um Silver
FSC0H_D_SP UMC 0.13um HS/FSG Logic process synchronous Via-1 ROM memory compiler. Memory_IP 0.13um Platinum
FSC0H_L_SP UMC 0.13um Logic HS FSG process low power synchronous VIA1 programmed ROM memory compiler. Memory_IP 0.13um Platinum
FSC0I_A_SP UMC 0.13um CMOS image sensor process synchronous Via 1 ROM memory compiler. Memory_IP 0.13um Silver
FSC0L_D_SP UMC 0.13um 1P8M 1.2V Low Leakage logic process synchronous VIA1 ROM memory compiler. Memory_IP 0.13um Platinum
FSC0U_D_SP UMC 0.13um 1P8M 1.2V logic fusion process synchronous VIA1 ROM memory compiler. Memory_IP 0.13um Gold
FSD0A_A_SP UMC 90nm/Low-K SP-RVT VIA1 Programmable ROM Compiler. Memory_IP 90nm Platinum
FSD0I_A_SP UMC 90CIS 1P3M Via ROM compiler Memory_IP 90nm Silver Minus
FSD0K_A_SP UMC 90nm Logic process low-leakage synchronous Contact VIA1 memory compiler. Memory_IP 90nm Silver
FSE0A_A_SP UMC 65nm SPRVT Logic process standard synchronous VIA1 ROM memory compiler Memory_IP 65nm Silver
FSE0K_A_SP UMC 65nm Logic LL RVT (Low K) process standard synchronous Via-1 ROM memory compiler Memory_IP 65nm Silver
FSF0A_A_SP UMC 55nm SP LowK Logic Process standard synchronous Via-1 ROM memory compiler. Memory_IP 55nm Silver
FSF0F_A_SP UMC 55nm EFLASH Process Via ROM Memory complier Memory_IP 55nm Bronze
FSF0L_A_SP UMC 55nm LP Logic Process Via1 ROM Memory Compiler Memory_IP 55nm Silver
FSF0L_L_SP UMC 55nm LP/Low-k PG Via1 ROM compiler Memory_IP 55nm Silver Minus
FSH0L_A_SP UMC 40 LP/RVT LowK Logic Process Via1 ROM Memory Compiler Memory_IP 40nm Silver
FSH0L_B_SP UMC 40nm LP Logic Process Via ROM compiler with WL booster Memory_IP 40nm Silver
FSJ0C_B_SP 28HPC Process Standard Synchronous Feature ROM Memory Compiler. Memory_IP 28nm Bronze
FSJ0C_L_SP UMC 28nm HPC Process PG Via ROM Compiler Memory_IP 28nm Silver Minus
FSJ0L_A_SP UMC 28nm HLP/Low-K Via ROM compiler Memory_IP 28nm Contact Sales
 
FSL0A_D_SP UMC 153nm Mixed-Mode/Logic process standard synchronous Via1 ROM memory compiler. Memory_IP 0.153um Silver
FSP0A_D_SP UMC 0.162um Logic GII process standard synchronous Via-1 programmable ROM memory compiler. Memory_IP 0.162um Silver
 
FSR0B_D_SP UMC 0.11um HS/ALE Logic Process synchronous via-1 ROM memory compiler Memory_IP 0.11um Platinum
FSR0F_C_SP UMC 0.110um eFlash HS process Via1 ROM compiler Memory_IP 0.11um Silver
FSR0H_D_SP UMC 0.11um High Speed Logic process standard synchronous Via-1 ROM memory compiler. Memory_IP 0.11um Platinum
FSR0I_A_SP UMC 0.11um CIS Process 1P3M VIA1 ROM Memory Compiler Memory_IP 0.11um Silver
FSR0K_D_SP UMC 0.11um LL/ALE (AL-Enhancement) Logic Process standard synchronous Via-1 ROM memory compiler Memory_IP 0.11um Silver
FSR0L_D_SP UMC 0.11um LL process synchronous Via-1 ROM memory compiler. Memory_IP 0.11um Gold
FSR0P_A_SP 110AE eFlash LL Process Via1 ROM compiler Memory_IP 0.11um Silver
FSR0T_D_SP UMC 0.11um SP/ALE (AL-Enhancement) Logic Process standard synchronous Via-1 ROM memory compiler. Memory_IP 0.11um Silver
 
Memory Compiler > ROM
> VIA1 ROM > VIA1 ROM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSF0F_A_SPHVT UMC 55nm eFlash Via1 ROM compiler with HVT Memory_IP 55nm Silver
FSF0G_W_SPHVT UMC 55nm embedded flash and embedded e2prom ultra low power split-gate via 1 ROM compiler with well bias Memory_IP 55nm Bronze
FSF0U_A_SPHVT UMC 55nm ULP Low-K process HVT via1 ROM Memory_IP 55nm Silver Minus
FSF0U_W_SPHVT UMC 55nm ULP/LowK Process via1 ROM compiler well bias Memory_IP 55nm Silver Minus
FSF0V_A_SPHVT UMC 55nm EHV PeriHVT Via1 ROM Compiler Memory_IP 55nm Silver
FSH0U_A_SPHVT UMC 40nm ultra low power via1 ROM complier Memory_IP 40nm Bronze
FSH0U_L_SPHVT UMC 40nm uLP process ULL Via1 ROM compiler Memory_IP 40nm Bronze
FSJ0C_L_SPHVT UMC 28nm HPC Logic Process Via ROM Low Power Compiler with HVT peripheral Memory_IP 28nm Bronze
FSJ0P_A_SPHVT UMC 28nm logic-mixed MODE28N-HPCUP synchronous Contact ROM memory compiler. Memory_IP 28nm Contact Sales
 
FST0J_A_SPHVT UMC 80nm LL/eHV Process synchronous Via ROM memory compiler Memory_IP 80nm Bronze
 
Memory Compiler > ROM
> VIA1 ROM > VIA1 ROM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_B_SPLVT UMC 40nm LP Logic Process Via ROM compiler with peri LVT and WL booster Memory_IP 40nm Silver
FSJ0C_L_SPLVT UMC 28nm HLC Logic process PG-Via1 ROM Compiler with LVT Memory_IP 28nm Bronze
 
Memory Compiler > ROM
> VIA1 ROM > VIA1 ROM, Peri uHVT 
Cell Name Descriptions Type Process Gradation Literature
FSF0G_W_SPUHVT UMC 55nm embedded flash and embedded e2prom ultra low power splite-gate synchronous via1 rom complier with well bias Memory_IP 55nm Bronze
FSF0U_W_SPUHVT UMC 55nm ULP/LowK Process via ROM compiler for well bias Memory_IP 55nm Silver Minus
 
Memory Compiler > ROM
> VIA1 ROM > VIA1 ROM, Sleep Mode 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_L_SP UMC 40LP Via1 ROM compiler with Sleep mode Memory_IP 40nm Silver
 
Memory Compiler > ROM
> VIA1 ROM > VIA1 ROM, Sleep Mode, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_L_SPLVT UMC 40LP via1 ROM compiler with Sleep mode & peri LVT Memory_IP 40nm Silver
 
Memory Compiler > ROM
> VIA2 ROM > VIA2 ROM 
Cell Name Descriptions Type Process Gradation Literature
FS70A_B_RC UMC 0.5um Logic process standard asynchronous VIA2 programmed ROM memory compiler. Memory_IP 0.5um Platinum
FS80A_B_RC UMC 0.35um Logic process standard asynchronous VIA2 programmed ROM memory compiler. Memory_IP 0.35um Platinum
FS90A_B_SC UMC 0.25um Logic process standard synchronous VIA2 programmed ROM memory compiler. Memory_IP 0.25um Platinum
FS90A_B_SO UMC 0.25um Logic process standard synchronous low power VIA2 programmed ROM memory compiler. Memory_IP 0.25um Platinum
FS90A_C_SC UMC 0.25um Logic process standard synchronous VIA2 programmable ROM memory compiler. Memory_IP 0.25um Gold
FSB0G_A_SC UMC 0.15um SP Logic process standard synchronous VIA2 programmed ROM memory compiler. Memory_IP 0.15um Silver
 
Memory Compiler > TCAM SRAM
> High Density TCAM 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_A_SF UMC 40nm LP process standard synchronous high density TCAM memory compiler. Memory_IP 40nm Bronze
FSJ0C_A_SFLVT UMC 28HPC process standard synchronous high density TCAM memory compiler Memory_IP 28nm Silver Minus
 
Memory Compiler > TCAM SRAM
> High Density TCAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_A_SFLVT UMC 40nm LP Logic Process TCAM with LVT peripheral memory compiler Memory_IP 40nm Bronze