1-Port SRAM

Updated On:2018-04-21
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > Asynchronous High Density 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FG70A_A_RS UMC 0.45um Logic process standard gate array asynchronous high density single port SRAM memory compiler. Memory_IP 0.45um Silver
FS70A_B_RH UMC 0.5um Logic process standard asynchronous high density single port SRAM memory compiler. Memory_IP 0.5um Platinum
FS80A_A_RH UMC 0.35um Logic process standard asynchronous high density single port SRAM memory compiler. Memory_IP 0.35um Platinum
FS80A_B_RH UMC 0.35um Logic process standard asynchronous high density single port SRAM memory compiler. Memory_IP 0.35um Platinum
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > Asynchronous Low Power 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FS70A_B_RA UMC 0.5um Logic process standard asynchronous low density low power single port SRAM memory compiler. Memory_IP 0.5um Platinum
FS80A_A_RA UMC 0.35um Logic process standard asynchronous low density low power single port SRAM memory compiler. Memory_IP 0.35um Platinum
FS80A_B_RA UMC 0.35um Logic process standard asynchronous low density low power single port SRAM memory compiler. Memory_IP 0.35um Platinum
FS90A_B_RA UMC 0.25um Logic process standard asynchronous low density low power single port SRAM memory compiler. Memory_IP 0.25um Platinum
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density & Low Power 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSF0F_L_SH UMC 55nm eFlash process process synchronous low power feature RVT peripheral high density single port SRAM compiler. Memory_IP 55nm Bronze
FSF0F_L_SHRED UMC 55nm eFlash process synchronous low power feature RVT peripheral high density single port SRAM compiler with row redundancy. Memory_IP 55nm Bronze
FSF0L_L_SH UMC 55um LP Low-K process ULL Singal-Port SRAM Compiler Memory_IP 55nm Silver
FSF0L_L_SHRED UMC 55um LP Low-K process Singal-Port SRAM Compiler with RED feature Memory_IP 55nm Silver
FSH0L_L_SH ULL Single Port SRAM ,UMC 40nm LP process. Memory_IP 40nm Silver
FSH0L_L_SHRED ULL Single Port SRAM with row redundancy , UMC 40nm LP Process. Memory_IP 40nm Silver Minus
FSH0U_B_SH UMC 40nm Low K Ultra Low Power Logic Process High-Density Single Port SRAM Compiler Memory_IP 40nm Contact Sales
FSJ0C_L_SH UMC 28nm HPC Logic Process PG Single Port SRAM memory compiler Memory_IP 28nm Silver Minus
FSJ0C_L_SHR1 UMC 28nm HPC process standard synchronous high density single port low power SRAM memory compiler with row redundancy Memory_IP 28nm Bronze
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density & Low Power 1PSRAM, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSF0F_L_SHHVT UMC 55nm eFlash Single-Port SRAM compiler with Power gating /HVT Memory_IP 55nm Silver
FSF0F_L_SHHVTRED UMC 55nm eFlash Single-Port SRAM with Row redundancy/HVT/Power -gating Memory_IP 55nm Silver
FSF0G_L_SHHVT UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler. Memory_IP 55nm Bronze
FSF0G_L_SHHVTRED UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler. Memory_IP 55nm Bronze
FSF0G_W_SHUHVT UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler. Memory_IP 55nm Bronze
FSF0U_L_SHHVT UMC 55nm ULP/LowK process Single-Port SRAM Memory_IP 55nm Silver Minus
FSF0U_L_SHHVTRED UMC 55nm ULP Low-K process, Single-Port SRAM with Row repair & periphery HVT Memory_IP 55nm Silver
 
FSH0L_L_SHHVT ULL Single Port SRAM with peri HVT, UMC 40nm LP process. Memory_IP 40nm Bronze
FSH0L_L_SHHVTRED ULL Sigle Port SRAM with HVT Row redundancy, UMC 40nm LP process. Memory_IP 40nm Silver Minus
FSH0L_L_SHLVT UMC 40nm LP/LVT SP-SRAM compiler with peri-LVT and Power gating Memory_IP 40nm Bronze
FSH0L_L_SHLVTRED UMC 40nm LP/LVT SP-SRAM compiler with power gating & row redundancy Memory_IP 40nm Bronze
FSJ0C_L_SHHVT UMC 28nm HPC Logic Process PG Single-Port SRAM with HVT memory compiler Memory_IP 28nm Bronze
FSJ0C_L_SHHVTR1 UMC 28nm HPC process standard synchronous HVT periphery high density single port low power SRAM memory compiler with row redundancy Memory_IP 28nm Bronze
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density & Low Power 1PSRAM, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_L_SHLVT UMC 28nm HPC Logic Process PG Single Port SRAM with LVT memory compiler Memory_IP 28nm Bronze
FSJ0C_L_SHLVTR1 UMC 28nm HPC process standard synchronous LVT periphery high density single port low power SRAM memory compiler with row redundancy Memory_IP 28nm Bronze
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density & Ultra Low Power 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSH0U_B_SHHVT UMC 40nm Low K Ultra Low Power Logic Process High-Density Single Port SRAM Compiler Memory_IP 40nm Contact Sales
FSH0U_B_SHRED UMC 40nm Low K Ultra Low Power Logic Process High-Density Single Port SRAM Compiler Memory_IP 40nm Contact Sales
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FS70A_B_SH UMC 0.5um Logic process standard synchronous high density single port SRAM memory compiler. Memory_IP 0.5um Platinum
FS80A_A_SH UMC 0.35um Logic process standard synchronous high density single port SRAM memory compiler. Memory_IP 0.35um Gold
FS80A_B_SH UMC 0.35um Logic process standard synchronous high density single port SRAM memory compiler. Memory_IP 0.35um Platinum
FS90A_B_SH UMC 0.25um Logic process standard synchronous high density single port SRAM memory compiler. Memory_IP 0.25um Platinum
FS90A_C_SH UMC 0.25um Logic process standard synchronous high density single port SRAM memory compiler. Memory_IP 0.25um Platinum
FSA0A_C_SU UMC 0.18um Logic GII process standard synchronous high speed single port SRAM memory compiler. Memory_IP 0.18um Platinum
FSA0A_D_SL UMC 0.18um Logic GII process synchronous High Density, Low Power mini single port SRAM Memory_IP 0.18um Platinum
FSA0F_A_SL UMC 0.18um e-flash GII process standard synchronous single port SRAM memory compiler. Memory_IP 0.18um Silver
FSA0F_B_SL UMC 0.18um eFlash process GII 4.0um2 Single Port SRAM Compiler Memory_IP 0.18um Silver
FSA0I_A_SL UMC 0.18um CIS process synchronous high density single port SRAM memory compiler. Memory_IP 0.18um Silver
FSA0L_A_SH UMC 0.18um Logic LL process standard synchronous high density single port SRAM memory compiler. Memory_IP 0.18um Silver
FSA0L_D_SL UMC 0.18um logic process high density, low power, mini area, single port SRAM compiler Memory_IP 0.18um Silver
FSA0M_A_SU UMC 0.18um mixed-mode process standard synchronous high density single port SRAM memory compiler. Memory_IP 0.18um Silver
FSA0V_A_SU UMC 0.18um high voltage 1.8V process synchronous high density single port SRAM memory compiler. Memory_IP 0.18um Silver
FSB0G_A_SH UMC 0.15um SP Logic process standard synchronous high density single port SRAM memory compiler. Memory_IP 0.15um Silver
FSC0G_D_SH UMC 0.13um Logic SP (FSG) process high density synchronous high density single port SRAM memory compiler. Memory_IP 0.13um Silver
FSC0H_D_SH UMC 0.13um Logic HS (FSG) process high density synchronous single port SRAM memory compiler. Memory_IP 0.13um Platinum
FSC0H_L_SH UMC 0.13um HS/FSG standard process synchronous high density low power single port SRAM memory compiler. Memory_IP 0.13um Platinum
FSC0I_A_SH UMC 0.13um CMOS image sensor process synchronous high density single port SRAM memory compiler. Memory_IP 0.13um Silver
FSC0L_D_SH UMC 0.13um Logic LL (FSG) process high density synchronous high density single port SRAM memory compiler. Memory_IP 0.13um Platinum
FSC0U_D_SH UMC 0.13um HS/LL fusion (FSG) process high density synchronous high density single port SRAM memory compiler. Memory_IP 0.13um Silver
FSD0A_A_SH UMC 90nm Logic process SP/low-k synchronous high density single port SRAM memory compiler Memory_IP 90nm Gold
FSD0A_A_SHRED UMC 90nm SP/Low-K Logic Process Synchronous High Density Single Port SRAM Compiler With Redundancy Memory_IP 90nm Silver
FSD0A_B_SH UMC 90nm SP/RVT Low-K Logic Process High Density Single Port 6T SRAM Memory Complier Memory_IP 90nm Platinum
FSD0A_B_SHRED UMC 90nm SP/RVT Low-K Logic Process Single Port SRAM (Introduce Redundancy feature to the existing FSD0A_B_SH) Memory_IP 90nm Silver
FSD0A_L_SH UMC 90nm SP Low-K Logic Process low power synchronous high density single port SRAM memory compiler. Memory_IP 90nm Bronze
FSD0I_A_SH UMC 90CIS 1P3M SP-SRAM compiler Memory_IP 90nm Silver Minus
FSD0I_A_SHRED 90CIS with Row redundancy SP-SRAM,UMC 90nm CIS Image Sensor Process. Memory_IP 90nm Bronze
FSD0K_A_SH UMC 90nm LL/RVT Synchronous high density one port SRAM memory compiler. Memory_IP 90nm Silver
FSD0K_A_SHRED UMC 90nm LL/RVT LowK Logic Process Synchronous High Density Single Port SRAM Compiler With Redundancy Memory_IP 90nm Silver
FSD0K_B_SH UMC 90nm LL Low-K RVT process synchronous single port SRAM memory compiler Memory_IP 90nm Silver
FSD0K_B_SHRED UMC 90nm LL/RVT Logic process standard synchronous high density single port SRAM memory compiler with redundancy feature. Memory_IP 90nm Silver
FSD0K_L_SH UMC 90nm Logic process low leakage devices synchronous Low-Power single port hihg density memory compiler. Memory_IP 90nm Silver
FSE0A_A_SH UMC 65nm SP LowK Logic Process standard synchronous high density single port SRAM memory compiler. Memory_IP 65nm Silver
FSE0A_A_SHRED UMC 65nm SP LowK Logic Process standard synchronous high density single port SRAM with redundaycy memory compiler. Memory_IP 65nm Silver
FSE0K_A_SH UMC 65nm LL/RVT LowK Logic Process 1-port high density memory compiler Memory_IP 65nm Silver
FSE0K_A_SHRED UMC 65nm LL/RVT LowK Process synchronous high density, single port SRAM compiler with the row redundancy. Memory_IP 65nm Silver
FSF0A_A_SH UMC 55nm SP Low_K Logic process standard synchronous high density single port SRAM memory compiler. Memory_IP 55nm Silver
FSF0A_A_SHRED UMC 55nm SP Low_K Logic process standard synchronous high density single port SRAM memory compiler with row-pair redundancy. Memory_IP 55nm Silver
FSF0A_B_SH UMC 55nm SP LowK Logic Process Synchronous One-Port SRAM using 0.425 bit cell Memory Compiler Memory_IP 55nm Silver
FSF0A_B_SHRED 55SP SPSRAM with row redundancy Memory_IP 55nm Silver
FSF0A_H_SH UMC 55nm SP/RVT LowK Logic Process standard synchronous Low Power (PG-DC) using 0.425 bit cell single port SRAM memory compiler. Memory_IP 55nm Silver
FSF0A_L_SH UMC 55nm SP LowK Logic Process low power synchronous high density single port SRAM memory compiler Memory_IP 55nm Silver
FSF0A_L_SHRED UMC 55nm SP LowK Logic Process low power synchronous high density single port SRAM memory compiler with redundancy Memory_IP 55nm Silver
FSF0A_N_SH UMC 55nm SP/RVT+HVT LowK Logic Process standard synchronous high density single port SRAM memory compiler. Memory_IP 55nm Silver
FSF0F_A_SH UMC 55nm eFlash Single-Port SRAM memory compiler Memory_IP 55nm Bronze
FSF0L_A_SH UMC 55nm LP LowK Logic Process Synchronous Single Port SRAM Memory Compiler Memory_IP 55nm Silver
FSF0L_A_SHRED UMC 55nm LP LowK Logic Process Synchronous SPRAM memory compiler with RED feature Memory_IP 55nm Silver
FSF0V_A_SH UMC 55nm eHV process;Single-Port SRAM compiler Memory_IP 55nm Silver Minus
FSF0V_A_SHRED UMC 55nm eHV process ; Single-Port SRAM compiler with Row redundancy Memory_IP 55nm Bronze
FSH0L_B_SH UMC 40nm LP/HVT Logic Process with 6TSRAM (0.242 mm2) One Port SRAM Memory Compiler Memory_IP 40nm Silver
FSH0L_B_SHRED UMC 40nm LP Logic Process Single Port SRAM memory compiler with row redundancy Memory_IP 40nm Silver
FSH0L_D_SH UMC 40nm Low Power Process SP-SRAM with 213 bit cell Memory_IP 40nm Silver Minus
FSH0L_D_SHRED UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell Memory_IP 40nm Bronze
FSH0L_H_SH UMC 40nm Low Power Process Single-Port SRAM 213cell with power gating Memory_IP 40nm Silver Minus
FSH0L_H_SHRED UMC 40nm Low Power Process PG SP-SRAM with Row redundancy for 213 bit cell Memory_IP 40nm Bronze
FSH0L_K_SH UMC 40nm Low Power Process Single-Port SRAM for dual power rail Memory_IP 40nm Bronze
FSH0L_L_SYHVT UMC 40nm LP with power gating & peri-HVT 1PRF Memory_IP 40nm Contact Sales
 
FSH0U_L_SYHVT UMC 40nm uLP process ULL One Port Register File memory compiler Memory_IP 40nm Bronze
FSJ0C_B_SH UMC 28nm Logic process standard synchronous RVT periphery high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0C_B_SHR1 UMC 28nm Logic process standard synchronous RVT periphery high density single port SRAM memory compiler with row redundancy. Memory_IP 28nm Bronze
FSJ0C_D_SH UMC 28nm HPC Logic Process Ultra High Density Single-Port SRAM Memory Compiler Memory_IP 28nm Silver Minus
FSJ0G_B_SH UMC 28nm HPM process standard synchronous high density single port SRAM memory compiler Memory_IP 28nm Silver Minus
FSJ0L_B_SH High Density Single Port SRAM, UMC 28nm HLP process Memory_IP 28nm Silver Minus
FSJ0L_B_SHC1 UMC 28nm HLP process standard synchronous high density single port SRAM memory compiler. Memory_IP 28nm Contact Sales
 
FSJ0L_B_SHR1 UMC 28nm HLP standard synchronous high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0L_B_SHR1C1 UMC 28nm HLP process standard synchronous High density single port SRAM memory compiler. Memory_IP 28nm Contact Sales
 
FSL0A_D_SL UMC 0.153um Mixed-Mode/Logic Process High Density, Low Power mini single port SRAM (porting of FSA0A_D_SL) Memory_IP 0.153um Silver
FSP0A_D_SL UMC 0.162um Logic GII process standard synchronous high density single port SRAM memory compiler. Memory_IP 0.162um Silver
 
FSP0J_A_SL UMC 0.162um eFalsh/LL Single-Port SRAM memory compiler Memory_IP 0.162um Bronze
FSR0A_A_SH 0.11um EE2PROM/LL 1.5v High density Single Port SRAM compiler Memory_IP 0.11um Silver Minus
FSR0B_B_SH UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process 1.41um2 Cell Single port SRAM compiler Memory_IP 0.11um Silver
FSR0B_D_SH UMC 0.11um HS/ALE logic process standard synchronous High-density single port SRAM memory compiler Memory_IP 0.11um Platinum
FSR0F_C_SH UMC 0.11um eFlash HS process ; Single-Port SRAM Memory Compiler Memory_IP 0.11um Silver
FSR0H_B_SH UMC 0.11um HS/FSG Logic Process;1.41um2 bit cell Single-Port SRAM Memory Compiler Memory_IP 0.11um Silver
FSR0H_D_SH UMC 0.11um HS Logic process synchronous, high density single port memory compiler Memory_IP 0.11um Gold
FSR0K_B_SH UMC 0.11um LL/AE (AL Advanced Enhancement) Logic Process Single Port SRAM compiler with 141 bit cell Memory_IP 0.11um Silver
FSR0K_D_SH UMC 0.11um LL/ALE Logic Process standard synchronous high density single port SRAM memory compiler. Memory_IP 0.11um Silver
FSR0L_D_SH UMC 0.11um Low Leakage Process Synchronous High Density Single-Port SRAM Compiler Memory_IP 0.11um Gold
FSR0P_A_SH 110AE eFlash LL SPSRAM Memory_IP 0.11um Silver
FSR0T_B_SH UMC 0.11um SP/AE Logic Process Synchronous Single-Port SRAM Memory compiler with 1.41um2 bit cell Memory_IP 0.11um Silver
FSR0T_D_SH UMC 0.11um SP/AE (AL Advance Enhancement) Logic Process standard synchronous High-density single port SRAM memory compiler. Memory_IP 0.11um Silver
FSR0U_A_SH UMC 0.11um Embedded High Voltage Mask Reduction AL Process standard synchronous high density single port SRAM memory compiler. Memory_IP 0.11um Bronze
FSR0V_A_SH UMC 0.11um HV Process 1.35um2 single port SRAM compiler Memory_IP 0.11um Silver
FSR0X_A_SH UMC 0.11um eFlash SP process; Single-Port SRAM compiler Memory_IP 0.11um Silver Minus
FST0J_A_SH UMC 80nm HV Process Single-Port SRAM Memory Compiler Memory_IP 80nm Silver
FST0J_A_SHRED UMC 80nm HV Process Single-Port SRAM Memory Compiler with Redundancy Memory_IP 80nm Silver
FST0J_L_SH UMC 80nm HV Process PG Single-Port SRAM Memory Compiler Memory_IP 80nm Silver Minus
FST0J_L_SHRED UMC 80nm HV Process Single-Port SRAM Memory Compiler with redundancy Memory_IP 80nm Bronze
FST0W_B_SH UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler. Memory_IP 80nm Silver Minus
FST0W_B_SHB4 UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler. Memory_IP 80nm Bronze
 
FST0W_B_SHRED UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler with redundancy. Memory_IP 80nm Silver Minus
FST0W_B_SHREDB4 UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler. Memory_IP 80nm Bronze
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM, Peri H/LVT 
Cell Name Descriptions Type Process Gradation Literature
FSF0V_B_SHHLVT UMC 55nm eHV Process Single Port SRAM Memory Compiler with Peripheral H/LVT using 277 bit-cell Memory_IP 55nm Silver Minus
FSF0V_B_SHHLVTRED UMC 55nm eHV Process Single Port SRAM with row redundancy for 277cell Memory_IP 55nm Bronze
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM, Peri H/RVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_D_SHHVTR1 UMC 28nm HPC Process Synchronous HVT/RVT Periphery High Density Single Port SRAM Memory Compiler with Row Redundancy Memory_IP 28nm Bronze
FSN0U_D_SHHRVT UMC 22nm ULP UHD SPSRAM compiler Memory_IP 22nm Contact Sales
 
FSN0U_D_SHHVT UMC 22nm ULP UHD SPSRAM compiler Memory_IP 22nm Contact Sales
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSF0F_A_SHHVT 55nm eFlash with Peri HVT SP-SRAM compiler Memory_IP 55nm Silver
FSF0F_A_SHHVTRED UMC 55nm eFlash with Peri HVT & RED SP-SRAM Memory_IP 55nm Silver
FSF0F_A_SHRED UMC 55nm EFLASH Processy Single-Port SRAM with row repair Memory complier Memory_IP 55nm Bronze
FSF0G_A_SHHVT UMC 55nm eflash/ulp process standard synchronous high density single port SRAM memory compiler. Memory_IP 55nm Bronze
FSF0G_A_SHHVTRED UMC 55nm SST/ulp Logic process standard synchronous high density single port SRAM memory compiler. Memory_IP 55nm Bronze
FSF0G_W_SHHVT UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler. Memory_IP 55nm Bronze
FSF0G_W_SHHVTRED UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler with row redundancy. Memory_IP 55nm Bronze
FSF0G_W_SHUHVTRED UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler with row redundancy. Memory_IP 55nm Bronze
FSF0I_A_SHHVT UMC 55nm CMOS Image Sensor 1P3M Process Single Port SRAM Memory Compiler with peri HVT Memory_IP 55nm Silver
FSF0I_A_SHHVTRED UMC 55nm CIS SP-SRAM with peri HVT and row redundancy Memory_IP 55nm Silver
FSF0U_A_SHHVT UMC 55nm ULP/LowK process Single-Port SRAM Memory_IP 55nm Silver Minus
 
FSF0U_A_SHHVTRED UMC 55nm ULP process , Single-Port SRAM with row repair and HVT Memory_IP 55nm Bronze
 
FSF0U_W_SHHVT UMC 55nm ULP/LowK Process Single-Port SRAM with well bias HVT Memory Compiler Memory_IP 55nm Silver Minus
FSF0U_W_SHHVTRED UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler Memory_IP 55nm Silver
FSF0U_W_SHUHVT UMC 55nm ULP/LowK Single-Port SRAM with Well Bias uHVT Memory_IP 55nm Silver Minus
FSF0U_W_SHUHVTRED UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler Memory_IP 55nm Bronze
FSF0V_A_SHHVT UMC 55EHV SP-SRAM compiler Memory_IP 55nm Silver
FSF0V_A_SHHVTRED UMC 55 EHV Process Single Port SRAM Memory Compiler with Row Redundancy Memory_IP 55nm Silver
FSH0L_D_SHHVT UMC 40nm LP Logic Process Single Port SRAM memory compiler using 213 bit -cell with peri-HVT Memory_IP 40nm Silver Minus
FSH0L_H_SHHVT UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-HVT Memory_IP 40nm Silver Minus
FSH0U_B_SHHVTRED UMC 40nm Low K Ultra Low Power Logic Process High-Density Single Port SRAM Compiler Memory_IP 40nm Contact Sales
FSH0U_L_SHHVT UMC 40nm uLP process ULL Single-Port SRAM Memory_IP 40nm Contact Sales
 
FSJ0C_D_SHHVT UMC 28nm HPC process synchronous HVT periphery high density single port SRAM memory compiler. Memory_IP 28nm Silver Minus
FSJ0P_D_SHHVT UMC 28HPC+ UHD SPSRAM compiler Memory_IP 28nm Contact Sales
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSF0V_A_SHLVT UMC 55nm HV SP-SRAM with peri LVT Memory_IP 55nm Silver
FSF0V_A_SHLVTRED UMC 55nm EHV Low Power Low-K process synchronous high density, single port SRAM compiler with row redundancy option. Memory_IP 55nm Silver
FSH0L_A_SEREDLVT UMC 40nm LP Logic Process Ultra High-Speed Single Port SRAM Memory compiler with Redundancy Memory_IP 40nm Silver Minus
FSH0L_B_SHLVT UMC 40nm LP Logic Process Single Port SRAM Compiler with LVT Periphery Memory_IP 40nm Silver
FSH0L_B_SHREDLVT UMC 40nm LP Logic Process Single Port SRAM Compiler LVT with row redundancy Memory_IP 40nm Silver
FSH0L_D_SHLVT UMC 40nm LP Logic Process Single Port SRAM Memory Compiler using 213 bit-cell with Peri-LVT Memory_IP 40nm Silver Minus
FSH0L_D_SHLVTRED UMC 40nm LP process synchronous high density (0.213LPHVT cell) single port SRAM compiler with row redundancy. Memory_IP 40nm Bronze
FSH0L_G_SELVT UMC 40um LP Logic Process High Speed Singl Port SRAM Compiler with 303RVT cell and Peri LVT Memory_IP 40nm Silver
FSH0L_H_SHLVT UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-LVT Memory_IP 40nm Silver Minus
FSH0L_H_SHLVTRED 40LP PG SP-SRAM LVT Peripheral with Row redundancy for 213 cell Memory_IP 40nm Bronze
FSJ0C_B_SHLVT UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler. Memory_IP 28nm Silver Minus
FSJ0C_B_SHLVTR1 UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0C_D_SHLVT UMC 28nm HPC process synchronous LVT periphery high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0C_D_SHLVTR1 UMC 28nm HPC Process Synchronous LVT/RVT Periphery High Density Single Port SRAM Memory Compiler with Row Redundancy Memory_IP 28nm Contact Sales
 
FSJ0L_B_SHLVT UMC 28nm HLP Logic process LVT standard synchronous high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0L_B_SHLVTC1 UMC 28nm HLP process standard LVT synchronous high density single port SRAM memory compiler. Memory_IP 28nm Contact Sales
 
FSJ0L_B_SHLVTR1 UMC 28nm HLP Logic process LVT standard synchronous high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0L_B_SHLVTR1C1 UMC 28nm HLP process LVT standard synchronous high density single port SRAM memory compiler. Memory_IP 28nm Contact Sales
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Speed 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FS70A_B_SU UMC 0.5um Logic process standard synchronous high density single port SRAM memory compiler. Memory_IP 0.5um Silver
FS80A_B_SU UMC 0.35um Logic process standard synchronous high speed single port SRAM memory compiler. Memory_IP 0.35um Platinum
FS90A_B_SU UMC 0.25um Logic process standard synchronous high speed single port SRAM memory compiler. Memory_IP 0.25um Platinum
FS90A_C_SU UMC 0.25um Logic process standard synchronous high speed single port SRAM memory compiler Memory_IP 0.25um Silver
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > Low Power 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FS80A_B_SA UMC 0.35um Logic process standard synchronous low density low power single port SRAM memory compiler. Memory_IP 0.35um Platinum
FS90A_B_SA UMC 0.25um Logic process standard synchronous low density low power single port SRAM memory compiler. Memory_IP 0.25um Platinum
FS90A_C_SA UMC 0.25um Logic Process standard synchronous single port Low Power SRAM memory compiler Memory_IP 0.25um Platinum
FS90A_C_SA UMC 0.25um Logic Process standard synchronous single port Low Power SRAM memory compiler Memory_IP 0.25um Platinum
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > Ultra High Density 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_D_SHR1 UMC 28nm HPC Logic Process Ultra High Density Single-Port SRAM Memory Compiler with Row Redundancy Memory_IP 28nm Contact Sales
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > Ultra High Speed 1PSRAM, 6T SRAM 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_A_SE UMC 28nm HPC Process Ultra High Speed Single-Port SRAM memory compiler Memory_IP 28nm Bronze
FSR0B_D_SE UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process Ultra High Speed Synchronous One Port SRAM Memory Compiler Memory_IP 0.11um Gold
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > Ultra High Speed 1PSRAM, 6T SRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_A_SELVT UMC 28nm HPC Process Ultra High Speed Single-Port SRAM Memory Compiler Memory_IP 28nm Silver Minus
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > Ultra High Speed 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSB0G_A_SE UMC 0.15um SP Logic process standard synchronousultra high speed single port SRAM memory compiler. Memory_IP 0.15um Silver
FSC0H_D_SE UMC 0.13um Logic HS (FSG) process synchronousultra high speed single port SRAM memory compiler. Memory_IP 0.13um Platinum
FSD0A_A_SE UMC 90nm SP-RVT/Low-k process synchronous ultra high speed SRAM compiler Memory_IP 90nm Platinum
FSD0T_A_SE UMC 90nm SPLVT ultra-high speed 1-port SRAM Memory_IP 90nm Contact Sales
 
FSE0A_A_SE UMC 65nm standard performance logic process synchronous extra high speed single port SRAM memory compiler. Memory_IP 65nm Silver Minus
FSF0A_A_SE UMC 55nm SP LowK Logic Process standard synchronous ultra high speed single port SRAM memory compiler. Memory_IP 55nm Silver
FSF0L_A_SE UMC 55nm Low-K/Low-Power Logic process synchronous ultra-high-speed single-port SRAM compiler. Memory_IP 55nm Bronze
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > Ultra High Speed 1PSRAM, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_A_SELVT UMC 40LP 303HVT cell /Peri-LVT Memory_IP 40nm Silver Minus