PowerSlash Core Cell Library

Updated On:2018-01-23
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Logic Libraries > PowerSlash Core Cell Library
> 12-Track 
Cell Name Descriptions Type Process Gradation Literature
FSF0F_GLS_POWERSLASH
_CORE
UMC 55nm eFlash/LVT Logic Process High Speed 12-track PowerSlash Kit cell library Library_Group 55nm Silver
FSH0L_GLS_POWERSLASH
_CORE
UMC 40nm LP/LVT Logic Process 12-track powerslash core cells Library_Group 40nm Bronze
FSH0L_GRS_POWERSLASH
_CORE
UMC 40nm LP/RVT LowK Logic Process 12-track Powerslash Cell Library Library_Group 40nm Bronze
FSJ0C_HHS_POWERSLASH
_CORE
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 12-track POWERSLASH cell library enhanced for routing (C35) Library_Group 28nm Contact Sales
 
FSJ0C_HLS_POWERSLASH
_CORE
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 12-track POWERSLASH cell library enhanced for routing (C35) Library_Group 28nm Bronze
FSJ0C_HRS_POWERSLASH
_CORE
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 12-track POWERSLASH cell library enhanced for routing (C35) Library_Group 28nm Contact Sales
 
 
Logic Libraries > PowerSlash Core Cell Library
> 12-Track > 12T HVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSF0F_GHS_POWERSLASH
_CORE
UMC 55nm eFlash/HVT Logic Process High Speed 12-track PowerSlash Kit cell library Library_Group 55nm Silver
FSF0L_GHS_POWERSLASH
_CORE
UMC 55nm LP/HVT LowK Logic Process 12-track generic core cell library Library_Group 55nm Silver
FSH0L_HHS_POWERSLASH
_CORE
UMC 40nm LP/HVT Logic Process 12-Track High Speed Cell PowerSlash Library (C40) Library_Group 40nm Silver
 
FSJ0C_GHS_POWERSLASH
_CORE
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 12-track PowerSlash cell library (C35) Library_Group 28nm Bronze
FSJ0L_GHS_POWERSLASH
_CORE
UMC 28nm Logic and Mixed-Mode HLP/HVT Process 12-track PowerSlash Cell library (C35) Library_Group 28nm Silver
 
Logic Libraries > PowerSlash Core Cell Library
> 12-Track > 12T LVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSF0L_GLS_POWERSLASH
_CORE
UMC 55nm LP/LVT LowK Logic Process 12-Tracks Powerslash Core Cell Library Library_Group 55nm Silver
FSH0L_HLS_POWERSLASH
_CORE
UMC 40nm LP/LVT Logic Process 12-Track High Speed Powerslash Core Cell Library Library_Group 40nm Silver
FSJ0C_GLS_POWERSLASH
_CORE
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 12-track PowerSlash cell library (C35) Library_Group 28nm Bronze
FSJ0L_GLS_POWERSLASH
_CORE
UMC 28nm Logic and Mixed-Mode HLP/LVT Process 12-track PowerSlash cell library (C35) Library_Group 28nm Silver
 
Logic Libraries > PowerSlash Core Cell Library
> 12-Track > 12T RVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSF0A_GRS_POWERSLASH
_CORE
UMC 55nm SP/RVT LowK Logic Process UHS library PSK cells Library_Group 55nm Bronze
 
FSF0F_GRS_POWERSLASH
_CORE
UMC 55nm eFlash/RVT Logic Process High Speed 12-track PowerSlash Kit cell library Library_Group 55nm Silver
FSF0L_GRS_POWERSLASH
_CORE
UMC 55nm LP/RVT LowK Logic Process 12-Tracks Powerslash Core Cell Library Library_Group 55nm Silver
FSH0L_HRS_POWERSLASH
_CORE
UMC 40nm LP/RVT Logic Process 12-Track High Speed PowerSlash Cell Library (C40) Library_Group 40nm Silver
FSJ0C_GRS_POWERSLASH
_CORE
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 12-track PowerSlash cell library (C35) Library_Group 28nm Bronze
 
FSJ0L_GRS_POWERSLASH
_CORE
UMC 28nm Logic and Mixed-Mode HLP/RVT Process 12-track Standard POWERSLASH core cell library (C35) Library_Group 28nm Silver