1-Port Register File

Updated On:2018-04-24
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density & Low Power 1PRF, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSC0H_L_SY UMC 0.13-micron 1P8M 1.2V high speed (HS) logic process synchronous low power single port register file SRAM compiler Memory_IP 0.13um Platinum
FSF0A_L_SY UMC 55nm SP LowK Logic process low power synchronous high density one port register file compiler Memory_IP 55nm Silver
FSF0U_L_SY UMC 55nm ULP Logic Process Synchronous Low Power Feature RVT Periphery One-port Register File Compiler Memory_IP 55nm Contact Sales
 
FSH0L_H_SY UMC 40nm Low Power Process One Port Register File with 213 cell Memory_IP 40nm Silver Minus
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density & Low Power 1PRF, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_H_SYHVT UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with HVT peripheral. Memory_IP 40nm Silver Minus
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density & Low Power 1PRF, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_H_SYLVT UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with LVT peripheral. Memory_IP 40nm Silver Minus
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSD0A_B_SYHVT UMC 90nm Standard Performance LowK Logic Process Synchronous high density single port register file SRAM memory compiler Memory_IP 90nm Silver
FSF0G_L_SYHVT UMC 55nm ULP-SST process PG One Port Register File for periphery HVT Memory_IP 55nm Bronze
 
FSF0G_W_SYHVT 55ULP-SST 1P-RF with forward biased and HVT periphery Memory_IP 55nm Bronze
 
FSF0G_W_SYUHVT 55ULP-SST 1P-RF with forward biased and UHVT periphery Memory_IP 55nm Bronze
 
FSJ0P_D_SYHVT UMC 28HPC+ 1PRF compiler with HVT peripheral Memory_IP 28nm Contact Sales
 
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FS90A_C_SY UMC 0.25um Logic process standard synchronous single port register file SRAM memory compiler Memory_IP 0.25um Platinum
FSA0A_C_SY UMC 0.18um Logic GII process standard synchronous single port register file SRAM memory compiler. Memory_IP 0.18um Platinum
FSA0L_A_SY UMC 0.18um Logic LL process standard synchronous single port register file SRAM memory compiler. Memory_IP 0.18um Platinum
FSA0M_A_SY UMC 0.18UM Mixed Mode/RF; One Port Register File Memory Compiler Memory_IP 0.18um Contact Sales
 
FSB0G_A_SY UMC 0.15um SP Logic process standard synchronous single port register file SRAM memory compiler. Memory_IP 0.15um Silver
FSC0G_D_SY UMC 0.13um Logic SP (FSG) process high density synchronous single port register file SRAM memory compiler. Memory_IP 0.13um Silver
FSC0H_D_SY UMC 0.13um Logic HS (FSG) process synchronous single port register file SRAM memory compiler. Memory_IP 0.13um Platinum
FSC0I_A_SY UMC 0.13um 2P4M 1.5V CMOS image sensor process synchronous single port register file SRAM compiler. Memory_IP 0.13um Silver
FSC0L_D_SY UMC 0.13um Logic LL (FSG) process high density synchronous single port register file SRAM memory compiler. Memory_IP 0.13um Platinum
FSC0S_A_SY UMC 130nm CIS(CMOS Image Sensor)Cu process 1PRF compiler Memory_IP 0.13um Silver
FSC0U_D_SY UMC 0.13um HS/LL fusion (FSG) process high density synchronous single port register file SRAM memory compiler. Memory_IP 0.13um Gold
FSD0A_A_SY UMC 90nm Logic standard performance process synchronous high density single port register file SRAM memory compiler. Memory_IP 90nm Platinum
FSD0A_B_SY UMC 90nm 1P9M SP/RVT low_K logic process synchronous one port register file Memory_IP 90nm Platinum
FSD0K_A_SY UMC 90nm LL/RVT Synchronous high density single port register file SRAM memory compiler Memory_IP 90nm Silver
FSD0K_B_SY UMC 90nm Low Leakage Low-K RVT process synchronous one-port register file memory compiler Memory_IP 90nm Silver
FSE0A_A_SY UMC 65nm standard performance process synchronous high density single port register file SRAM memory compiler. Memory_IP 65nm Silver
FSE0A_B_SY UMC 65nm SP LowK Logic Process synchronous single port register file SRAM memory compiler. Memory_IP 65nm Contact Sales
 
FSE0K_A_SY UMC 65nm LL/RVt (Low K) Logic process synchronous single port SRAM Memory_IP 65nm Silver
FSF0A_A_SY UMC 55nm SP Low_K Logic process standard synchronous high density one port register file compiler. Memory_IP 55nm Silver
FSF0A_B_SY UMC 55nm Standard Performance LowK Logic Process synchronous single port register file SRAM using 0.425 bit cell Memory Compiler Memory_IP 55nm Silver
FSF0A_H_SY UMC 55nm SP/RVT LowK Logic Process standard synchronous Low Power (PG-DC) using 0.425 bit cell Single Port Register File memory compiler. Memory_IP 55nm Silver
FSF0F_A_SY UMC 55nm eFlash peocess One Port Register File memory compiler Memory_IP 55nm Bronze
FSF0L_A_SY UMC 55nm LP Logic Process 0.425um2 bit cell One Port Register File Memory Compiler Memory_IP 55nm Silver
FSH0L_B_SY UMC 40nm LP/HVT Logic Process with 6TSRAM (0.242 mm2) 1-port Register File Memory Compiler Memory_IP 40nm Silver
FSH0L_G_SQLVT UMC 40nm LP Logic Process Ultra High Speed One-Port Register File Memory_IP 40nm Silver
FSH0L_L_SY 40LP 1PRF with Sleep/retention/Nap mode feature Memory_IP 40nm Silver
FSJ0C_B_SY UMC 28nm HPC process One Port Register File Memory_IP 28nm Silver Minus
FSJ0C_D_SY UMC 28nm HPC Logic Process Ultra High Density 1-Port Register File Memory Compiler Memory_IP 28nm Silver Minus
FSJ0L_B_SY UMC 28nm HLP/Low-k One Port Register File Memory_IP 28nm Silver Minus
 
FSJ0P_D_SY UMC 28nm HPC Plus Process Standard Synchronous High Density Single Port Register File Memory Compiler. Memory_IP 28nm Contact Sales
 
FSL0A_C_SY UMC 0.153um Mixed-Mode/Logic process standard synchronous high density single port register file SRAM memory compiler Memory_IP 0.153um Silver
FSL0M_A_SY UMC 0.153um Logic/Mixed-Mode 3.3V MR process standard synchronous one port register file SRAM memory compiler. Memory_IP 0.153um Contact Sales
 
FSP0A_C_SY UMC 0.162um Logic GII process synchronous high density single port register file SRAM memory compiler Memory_IP 0.162um Silver
 
FSP0J_A_SY UMC 0.162um eFalsh/LL One Port Register File memory compiler Memory_IP 0.162um Bronze
FSR0B_B_SY UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process 1.41um2 cell One Port Register File Memory Compiler Memory_IP 0.11um Silver
FSR0B_D_SY UMC 0.11um HS/ALE Logic Process standard synchronous high density single port register file SRAM memory compiler. Memory_IP 0.11um Platinum
FSR0F_C_SY 110AE eFlash HS process for 1PRF compiler Memory_IP 0.11um Silver
FSR0H_B_SY UMC 0.11um HS/FSG Logic Process;One Port Register File Memory Compiler. Memory_IP 0.11um Silver
 
FSR0H_D_SY UMC 0.11um HS Logic process synchronous single port register file memory compiler Memory_IP 0.11um Platinum
FSR0I_A_SY UMC 0.11um CMOS Image Sensor 2P3M process standard synchronous high density single port register file SRAM memory compiler. Memory_IP 0.11um Bronze
FSR0K_B_SY UMC 0.11um LL/AE (AL Advanced Enhancement) Logic Process 1.41um2 cell Single Port Register File (1PRF) Memory Compiler Memory_IP 0.11um Silver
FSR0K_D_SY UMC 0.11um LL/ALE Logic Process standard asynchronous high density single port register file SRAM memory compiler. Memory_IP 0.11um Silver
FSR0L_D_SY UMC 0.11um LL/FSG process synchronous single port register file SRAM memory compiler. Memory_IP 0.11um Gold
FSR0P_A_SY 110AE eFlash LL process 1PRF Memory_IP 0.11um Silver
FSR0T_B_SY UMC 0.11um SP/AE Logic Process Synchronous One Port Register File Memory Compiler with 1.41um2 bit cell Memory_IP 0.11um Silver
FSR0T_D_SY UMC 0.11um SP/AE (AL Advance Enhancement) Logic Process standard synchronous high density single port register file SRAM memory compiler. Memory_IP 0.11um Silver
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM, Peri HVT, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSF0F_A_SYHVT UMC 55nm eFlash with peri HVT 1PRF Memory_IP 55nm Silver
FSF0F_L_SYHVT UMC 55nm eFlash One Port Register File with power-gating Memory_IP 55nm Silver
FSF0U_A_SYHVT UMC 55nm ULP Low-K process One Port Register File for periphery HVT Memory_IP 55nm Silver Minus
FSF0U_L_SYHVT UMC 55nm ULP process PG-One Port Register File for periphery HVT Memory_IP 55nm Silver Minus
FSF0U_W_SYHVT UMC 55nm uLP LowK Logic Process One Port Register File with well bias & periphery HVT Memory_IP 55nm Silver Minus
FSH0U_A_SYHVT UMC 40nm uLP Logic Process 1-Port Register File with Peri-HVT Memory_IP 40nm Contact Sales
 
FSJ0C_D_SYHVT UMC 28HPC 1PRF compiler with HVT peripheral Memory_IP 28nm Bronze
FSJ0C_L_SYHVT UMC 28nm HPC Logic process PG-One Port Register File with HVT Memory_IP 28nm Bronze
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM, Peri HVT/SVT 
Cell Name Descriptions Type Process Gradation Literature
FSN0U_D_SYHVT UMC 22uLP Logic Process 1-Port Register File Memory Compiler with HVT+SVT peripherals Memory_IP 22nm Contact Sales
 
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSF0G_A_SYHVT UMC 55nm Embedded Flash and Embedded E2PROM Ultra Low Power Split-Gate Process Memory_IP 55nm Bronze
FSH0L_B_SYLVT UMC 40nm LP Logic Process single port register file memory compiler with LVT periphery Memory_IP 40nm Silver
FSH0L_L_SYLVT 40LP 1PRF with Sleep/Retention/Nap mode & peri LVT feature Memory_IP 40nm Silver
FSJ0C_B_SYLVT UMC 28nm HPC process One Port Register File with LVT Memory_IP 28nm Bronze
 
FSJ0C_D_SYLVT UMC 28HPC process 1PRF compiler with LVT peripheral Memory_IP 28nm Bronze
FSJ0L_B_SYLVT UMC 28nm HLP Logic Process One Port Register File with LVT Memory_IP 28nm Bronze
 
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM, Peri LVT, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_L_SYLVT UMC 28nm HPC Logic process PG One Port Register File with LVT Memory_IP 28nm Bronze
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM, Peri uHVT 
Cell Name Descriptions Type Process Gradation Literature
FSF0U_W_SYUHVT UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery Memory_IP 55nm Silver Minus
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSF0F_L_SY UMC 55nm EFLASH Process ULL One Port Register File Memory_IP 55nm Bronze
FSF0L_L_SY UMC 55um LP Low-K process One Port Register File compiler Memory_IP 55nm Silver
FSJ0C_L_SY UMC 28nm HPC Logic process PG One Port Register File Memory_IP 28nm Silver Minus
 
Memory Compiler > 1-Port Register File
> 6TSRAM > Ultra High Speed 1PRF, 6TSRAM  
Cell Name Descriptions Type Process Gradation Literature
FSH0L_D_SY UMC 40nm Low Power Process One Port Register File wit 213 cell Memory_IP 40nm Silver Minus
FSJ0C_A_SQ UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler Memory_IP 28nm Bronze
FSJ0L_A_SQ UMC 28nm Logic process standard synchronous Ultra High Speed Single Port Register File SRAM memory compiler. Memory_IP 28nm Bronze
 
Memory Compiler > 1-Port Register File
> 6TSRAM > Ultra High Speed 1PRF, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_D_SYHVT UMC 40nm LP Logic Process one-port register file for area optimize with HVT peripheral Memory_IP 40nm Silver Minus
FSH0V_D_SYHVT UMC 40nm embedded high voltage (eHV) low power Process standard synchronous high density single port register file SRAM memory compiler. Memory_IP 40nm Bronze
 
Memory Compiler > 1-Port Register File
> 6TSRAM > Ultra High Speed 1PRF, 6TSRAM, Peri HVT/RVT 
Cell Name Descriptions Type Process Gradation Literature
FSN0U_A_SQHVT UMC 22nm uLP logic process Synchronous HVT+RVT Periphery Ultra-High-Speed One-Port Register File Compiler Memory_IP 22nm Contact Sales
 
FSN0U_L_SZHVT UMC 22uLP Logic process 2PRF memory compiler with NAP/RET/SLP mode Memory_IP 22nm Contact Sales
 
 
Memory Compiler > 1-Port Register File
> 6TSRAM > Ultra High Speed 1PRF, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_D_SYLVT UMC 40nm LP Logic Process one-port register file for area optimize with LVT peripheral Memory_IP 40nm Silver Minus
FSJ0C_A_SQLVT UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler with periphery LVT Memory_IP 28nm Silver Minus
FSJ0C_L_SELVT Synchronous LVT Periphery Ultra-High-Speed Single-Port SRAM Compiler Memory_IP 28nm Bronze
FSJ0L_A_SQLVT UMC 28nm HLP/UHS 1PRF compiler with peri LVT Memory_IP 28nm Bronze
 
Memory Compiler > 1-Port Register File
> 6TSRAM > Ultra High Speed 1PRF, 6TSRAM, Peri LVT/RVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0P_A_SQHVT UMC 28nm Logic and Mixed-Mode High Performance Process Synchronous HVT+RVT Periphery Ultra-High-Speed One-Port Register File Compiler Memory_IP 28nm Contact Sales