1-Port SRAM

Updated On:2018-01-23
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSF0V_A_SHLVT UMC 55nm HV SP-SRAM with peri LVT Memory_IP 55nm Silver
FSF0V_A_SHLVTRED UMC 55nm EHV Low Power Low-K process synchronous high density, single port SRAM compiler with row redundancy option. Memory_IP 55nm Silver
FSH0L_A_SEREDLVT UMC 40nm LP Logic Process Ultra High-Speed Single Port SRAM Memory compiler with Redundancy Memory_IP 40nm Silver Minus
FSH0L_B_SHLVT UMC 40nm LP Logic Process Single Port SRAM Compiler with LVT Periphery Memory_IP 40nm Silver
FSH0L_B_SHREDLVT UMC 40nm LP Logic Process Single Port SRAM Compiler LVT with row redundancy Memory_IP 40nm Silver
FSH0L_D_SHLVT UMC 40nm LP Logic Process Single Port SRAM Memory Compiler using 213 bit-cell with Peri-LVT Memory_IP 40nm Silver Minus
FSH0L_D_SHLVTRED UMC 40nm LP process synchronous high density (0.213LPHVT cell) single port SRAM compiler with row redundancy. Memory_IP 40nm Bronze
FSH0L_G_SELVT UMC 40um LP Logic Process High Speed Singl Port SRAM Compiler with 303RVT cell and Peri LVT Memory_IP 40nm Silver
FSH0L_H_SHLVT UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-LVT Memory_IP 40nm Silver Minus
FSH0L_H_SHLVTRED 40LP PG SP-SRAM LVT Peripheral with Row redundancy for 213 cell Memory_IP 40nm Bronze
FSJ0C_B_SHLVT UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler. Memory_IP 28nm Silver Minus
FSJ0C_B_SHLVTR1 UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0C_D_SHLVT UMC 28nm HPC process synchronous LVT periphery high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0C_D_SHLVTR1 UMC 28nm HPC Process Synchronous LVT/RVT Periphery High Density Single Port SRAM Memory Compiler with Row Redundancy Memory_IP 28nm Contact Sales
 
FSJ0L_B_SHLVT UMC 28nm HLP Logic process LVT standard synchronous high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0L_B_SHLVTC1 UMC 28nm HLP process standard LVT synchronous high density single port SRAM memory compiler. Memory_IP 28nm Contact Sales
 
FSJ0L_B_SHLVTR1 UMC 28nm HLP Logic process LVT standard synchronous high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0L_B_SHLVTR1C1 UMC 28nm HLP process LVT standard synchronous high density single port SRAM memory compiler. Memory_IP 28nm Contact Sales