Dual-Port SRAM |
Updated On:2018-04-24 |
|
|
Memory Compiler > Dual-Port SRAM |
> 6TSRAM > High Density DPSRAM, 6TSRAM, Peri LVT, Power Gating |
Cell Name |
Descriptions |
Type |
Process |
Gradation |
Literature |
FSJ0C_L_SJLVT
|
UMC 28nm HPC process PG-Dual Port SRAM with LVT |
Memory_IP |
28nm |
Bronze
|
|
FSJ0C_L_SJLVTR1
|
UMC 28nm HPC process PG Dual Port SRAM with LVT |
Memory_IP |
28nm |
Bronze
|
|
|
|
 |
|
|
|
|