Dual-Port SRAM Updated On:2018-04-23

Gradation Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below, Platinum P Five (5) productions verified Gold G Mass production proven Silver S Silicon proven, Formal release Silver Minus S- Manufacturing onging Bronze B Pre-Silicon release

 

Memory Compiler > Dual-Port SRAM > 8TSRAM > High Density DPSRAM, 8TSRAM, Peri HVT  Cell Name Descriptions Type Process Gradation Literature FSF0V_A_SJHVT UMC 55nm EHV Dual Port SRAM Compiler with peri-HVT Memory_IP 55nm Silver Minus FSF0V_A_SJHVTRED UMC 55nm EHV Dual Port SRAM compiler with peri_HVT Memory_IP 55nm Bronze FSJ0C_A_SJHVT UMC 28nm HPC process Dual Port SRAM compiler Memory_IP 28nm Bronze FSJ0C_A_SJHVTR1 UMC 28nm HPC process Dual Port SRAM compiler Memory_IP 28nm Bronze FSJ0C_L_SJHVTR1 UMC 28HPC process standard synchronous high density dual port SRAM memory compiler. Memory_IP 28nm Bronze FSJ0P_A_SJHVT UMC 28nm HPC+ process dual port SRAM memory compiler with HVT+RVT peripheral Memory_IP 28nm Contact Sales