ROM

Updated On:2018-04-21
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Memory Compiler > ROM
> VIA1 ROM > VIA1 ROM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSF0F_A_SPHVT UMC 55nm eFlash Via1 ROM compiler with HVT Memory_IP 55nm Silver
FSF0G_W_SPHVT UMC 55nm embedded flash and embedded e2prom ultra low power split-gate via 1 ROM compiler with well bias Memory_IP 55nm Bronze
FSF0U_A_SPHVT UMC 55nm ULP Low-K process HVT via1 ROM Memory_IP 55nm Silver Minus
FSF0U_W_SPHVT UMC 55nm ULP/LowK Process via1 ROM compiler well bias Memory_IP 55nm Silver Minus
FSF0V_A_SPHVT UMC 55nm EHV PeriHVT Via1 ROM Compiler Memory_IP 55nm Silver
FSH0U_A_SPHVT UMC 40nm ultra low power via1 ROM complier Memory_IP 40nm Bronze
FSH0U_L_SPHVT UMC 40nm uLP process ULL Via1 ROM compiler Memory_IP 40nm Bronze
FSJ0C_L_SPHVT UMC 28nm HPC Logic Process Via ROM Low Power Compiler with HVT peripheral Memory_IP 28nm Bronze
FSJ0P_A_SPHVT UMC 28nm logic-mixed MODE28N-HPCUP synchronous Contact ROM memory compiler. Memory_IP 28nm Contact Sales
 
FST0J_A_SPHVT UMC 80nm LL/eHV Process synchronous Via ROM memory compiler Memory_IP 80nm Bronze