DDR

Updated On:2018-01-19
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR1 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR1A173HF0A DDR1/MDDR PHY CMD/ADDR BLOCK ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process Analog_IP 55nm Bronze
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR2 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR2A173HE0A DDR2/MDDR PHY CMD/ADDR BLOCK ; UMC 65nm 1.0V process with 2.5V device SP/RVT Lowk Logic Process Analog_IP 65nm Silver
FXDDR2A173HF0A DDR2/MDDR Combo PHY CMD ADDR block ; UMC 55nm SP/RVT Lowk Process with 2.5V device Analog_IP 55nm Silver
FXDDR2A174HE0A DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage ; UMC 65nm 1.0V with 2.5V Device SP/RVT LowK Logic Process Analog_IP 65nm Silver
FXDDR2A174HF0A DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage; UMC 55nm 1.0V with 2.5V device SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR2A200HC0H DDR2/MDDR Combo Command/Address Block ; UMC 0.13um HS/FSG Logic Process Analog_IP 0.13um Bronze
FXDDR2A200HE0L DDR2/DDR1/MDDR Combo Command/Address Block ; UMC 65nm LP/RVT LowK Logic Process Analog_IP 65nm Silver
FXDDR2A200HR0B Command/address block of 1:2 DDR2-PHY ; 0.11um HS/AE (AL Advanced Enhancement) Logic Process Analog_IP 0.11um Silver Minus
FXDDR2A200HR0H 1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process Analog_IP 0.11um Silver
 
FXDDRIIA171HC0H DDR2 PHY Command/Address Block ; UMC 0.13um HS/FSG Logic Process Analog_IP 0.13um Platinum
FXDDRIIA172HC0H DDR2 PHY Command/Address Block (for Chip Application); UMC 0.13um HS/FSG Logic Process Analog_IP 0.13um Silver
FXDDRIIA173HD0A_FTC DDR2-PHY command/address block for DRAM chip, BOAC ; UMC 90nm SP/RVT Low-K Logic Process Analog_IP 90nm Silver Minus
FXDDRIIA174HD0A DDR2-PHY Command/Address block; UMC 90nm SP/RVT Lowk Process Analog_IP 90nm Gold
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR3 PHY - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3AIO502EWHJ0C_F
TC
IO Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR ; UMC 28nm HPC/RVT Logic Process Analog_IP 28nm Contact Sales
 
FXDDR4AFC602HH0L Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR3/3L - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3A100HD0A DDR2/3 Combo Command /Address Block (with 2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Process Analog_IP 90nm Silver Minus
FXDDR3A100HH0L DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device Analog_IP 40nm Silver
FXDDR3A300HF0A Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3A300HF0L Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Silver Minus
FXDDR3A402HF0A Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3A403HF0A Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application;UMC 55nm SP/RVT LowK PROCESS. Analog_IP 55nm Silver
FXDDR3A412HF0L Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Bronze
FXDDR3A502HF0A Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Contact Sales
 
FXDDR3A502HH0L Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process Analog_IP 40nm Silver
FXDDR3A503HH0L DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
FXDDR3AFC502HH0L DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR4 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4AFC101HH0L DDR34 COMBO PHY ADDR Block for Solder bump Flip chip version ;UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
FXDDR4AFD612EWHJ0C Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version ; UMC 28nm Logic and Mixed-Mode Low-K HPC Process Analog_IP 28nm Contact Sales
 
FXDDR4AFD612HH0L Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version; UMC 40nm LP LVT/RVT LowK Logic Process Analog_IP 40nm Contact Sales
FXDDR4AFD612NSHJ0C Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version ; UMC 28nm Logic and Mixed-Mode Low-K HPC Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > LPDDR2 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3A412HF0A Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Bronze
FXLPDDR2A102HH0L_SIP 40nm LPDDR2-PHY command/address block for SIP Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > LPDDR3 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXLPDDR3AW101HH0L LPDDR3-PHY Command/address block for LightCo ; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales