DDR

Updated On:2018-04-25
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR1 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR1D173HF0A DDR1/MDDR PHY Data block ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process Analog_IP 55nm Bronze
 
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR2 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR2D172HR0B DDRII Data Block for Chip Application; UMC 0.11um HS/AE (AL Advance Enhancement) Logic Process Analog_IP 0.11um Bronze
 
FXDDR2D173HE0A DDR2/MDDR Combo PHY for Chip load usage ; UMC 65NM SP-RVT with 2.5V device LowK Logic Process Analog_IP 65nm Bronze
FXDDR2D173HF0A DDR2/MDDR COMBO PHY Data block for Chip usage ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process Analog_IP 55nm Silver
FXDDR2D174HE0A DDR2/MDDR PHY Data block ; UMC 65nm 1.0V with 2.5V device SP/RVT LowK Logic Process Analog_IP 65nm Silver
FXDDR2D174HF0A DDR2/MDDR Combo PHY data block ; UMC 55nm SP process with 2.5V device Analog_IP 55nm Silver
FXDDR2D200HC0H DDR2/MDDR Combo Data Block ; 0.13um Logic HS/FSG Logic Process Analog_IP 0.13um Bronze
FXDDR2D200HE0L DDR2/DDR1/MDDR Combo Data Block ; UMC 65nm LP/RVT LowK Logic Process Analog_IP 65nm Silver
FXDDR2D200HR0B Data block of 1:2 DDR2-PHY ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process Analog_IP 0.11um Silver Minus
FXDDR2D200HR0H 1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process Analog_IP 0.11um Silver
 
FXDDRIID171HC0H DDR2 PHY Data Block ;UMC 0.13um Logic HS/FSG Process Analog_IP 0.13um Gold
FXDDRIID172HC0H DDRII Data Block for Chip Application; UMC 0.13um HS/FSG Logic Process Analog_IP 0.13um Silver
FXDDRIID173HD0A_FTC DDR2-PHY data block with BOAC IO; UMC 90nm SP/RVT Lowk Logic Process Analog_IP 90nm Silver Minus
FXDDRIID174HD0A DDR2-PHY data block; UMC 90nm SP/RVT Lowk Process Analog_IP 90nm Gold
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR3 PHY - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3DIO502NSHJ0C_F
TC
IO Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR ; UMC 28nm HPC/RVT Logic Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR3/3L - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3D100HD0A DDR2/3 PHY Combo PHY data block (1.0v SP & 2.5V device); UMC 90nm SP/RVT LowK Logic Process Analog_IP 90nm Silver
FXDDR3D100HH0L DDR23 COMBO PHY Data Block ; UMC 40nm LP/RVT LowK Logic Process with 2.5V device Analog_IP 40nm Silver
FXDDR3D300HF0A Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3D300HF0A Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3D300HF0L Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Silver Minus
FXDDR3D402HF0A Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3D402HF0A Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3D403HF0A Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Silver
FXDDR3D412HF0L Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Bronze
FXDDR3D502HF0A Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Contact Sales
 
FXDDR3D502HH0L Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process Analog_IP 40nm Silver Minus
FXDDR3DFC502HH0L DDR3 Combo PHY Data Block for solder bump application; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
FXDDR3LTD102HH0L DDR3/DDR3L/LPDDR2 combo PHY ( not support DDR3 leveling function), data block;UMC 40nm LP/RVT LowK Logic Process . Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR4 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4D16FC101HH0L 40nm LP DDR3/4 LPDDR23 COMBO PHY DATA Block for Flip Chip usage Analog_IP 40nm Contact Sales
 
FXDDR4DFD612HH0L Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process Analog_IP 40nm Contact Sales
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR4 PHY - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4D16FC602HH0L Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Data Block > LPDDR2 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXLPDDR2D102HH0L_SIP 40nm LPDDR2-PHY data block for SIP Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Data Block > LPDDR3 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4DFD612EWHJ0C Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 28nm Logic and Mixed-Mode Low-K HPC Process Analog_IP 28nm Contact Sales
 
FXDDR4DFD612EWHJ0P Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 28nm Logic and Mixed-Mode Low-K HPC+ Process Analog_IP 28nm Contact Sales
 
FXDDR4DFD612NSHJ0C Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 28nm Logic and Mixed-Mode Low-K HPC Process Analog_IP 28nm Contact Sales
 
FXDDR4DFD612NSHJ0P Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 28nm Logic and Mixed-Mode Low-K HPC+ Process Analog_IP 28nm Contact Sales
 
FXLPDDR3D16W101HH0L 40nm LPDDR3-PHY Data block for LightCo ; UMC 40nm LP/LVT Logic Process Analog_IP 40nm Contact Sales