DDR

Updated On:2018-01-23
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR2 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR2D172HR0B DDRII Data Block for Chip Application; UMC 0.11um HS/AE (AL Advance Enhancement) Logic Process Analog_IP 0.11um Bronze
 
FXDDR2D173HE0A DDR2/MDDR Combo PHY for Chip load usage ; UMC 65NM SP-RVT with 2.5V device LowK Logic Process Analog_IP 65nm Bronze
FXDDR2D173HF0A DDR2/MDDR COMBO PHY Data block for Chip usage ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process Analog_IP 55nm Silver
FXDDR2D174HE0A DDR2/MDDR PHY Data block ; UMC 65nm 1.0V with 2.5V device SP/RVT LowK Logic Process Analog_IP 65nm Silver
FXDDR2D174HF0A DDR2/MDDR Combo PHY data block ; UMC 55nm SP process with 2.5V device Analog_IP 55nm Silver
FXDDR2D200HC0H DDR2/MDDR Combo Data Block ; 0.13um Logic HS/FSG Logic Process Analog_IP 0.13um Bronze
FXDDR2D200HE0L DDR2/DDR1/MDDR Combo Data Block ; UMC 65nm LP/RVT LowK Logic Process Analog_IP 65nm Silver
FXDDR2D200HR0B Data block of 1:2 DDR2-PHY ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process Analog_IP 0.11um Silver Minus
FXDDR2D200HR0H 1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process Analog_IP 0.11um Silver
 
FXDDRIID171HC0H DDR2 PHY Data Block ;UMC 0.13um Logic HS/FSG Process Analog_IP 0.13um Gold
FXDDRIID172HC0H DDRII Data Block for Chip Application; UMC 0.13um HS/FSG Logic Process Analog_IP 0.13um Silver
FXDDRIID173HD0A_FTC DDR2-PHY data block with BOAC IO; UMC 90nm SP/RVT Lowk Logic Process Analog_IP 90nm Silver Minus
FXDDRIID174HD0A DDR2-PHY data block; UMC 90nm SP/RVT Lowk Process Analog_IP 90nm Gold