IO Cell Library

Updated On:2018-01-23
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Logic Libraries > IO Cell Library
> Analog ESD IO Library > True 1.8V Analog ESD IO Library 
Cell Name Descriptions Type Process Gradation Literature
FOA0A_A33_T18_ANALOG
ESD_IO
UMC 0.18um GII Logic Process True 1.8V Analog ESD I/O Cell Library (move FSA0A_C IO cells to new IO library FOA0A_A33) Library_Group 0.18um Silver
FOA0A_O_T18_ANALOGES
D_IO
UMC 0.18um GII Logic Process 1.8V ANALOGESD IO with POC solution Library_Group 0.18um Silver
FOA0L_O_T18_ANALOGES
D_IO
UMC 0.18um LL Logic Process 1.8V ANALOGESD IO with POC solution Library_Group 0.18um Silver
FOH0L_PRS25_T18_ANAL
OGESD_LOWC_IO
1.8V analog ESD IO cells with low capacitor for UMC 40LP process Library_Group 40nm Contact Sales
 
FOJ0C_ORS18_T18_ANAL
OGESD_IO
UMC 28nm Logic and Mixed-Mode HPC Process, 1.8V Analog ESD IO cell Library Library_Group 28nm Bronze
 
FOJ0C_QRS18_T18_ANAL
OGESD_IO
UMC 28nm Logic and Mixed-Mode HPC Process, 1.8V Analog ESD IO cell PG_lib Library Library_Group 28nm Contact Sales
 
FOJ0L_ORS18_T18_ANAL
OGESD_IO
UMC 28nm Logic and Mixed-Mode HLP/RVT Process, 1.8V Analog ESD IO cell Library Library_Group 28nm Silver
FOJ0P_ORS18_T18_ANAL
OGESD_IO
UMC 28nm Logic and Mixed-Mode HPC+ Process, 1.8V Analog ESD IO cell Library Library_Group 28nm Contact Sales
 
FSA0A_C_T18_ANALOGES
D_IO
UMC 0.18um Logic GII process 1.8V analog ESD IO set. Library_Group 0.18um Silver
FSA0L_A_T18_ANALOGES
D_IO
UMC 0.13um Logic LL process 1.8V analog ESD IO set. Library_Group 0.18um Silver