DDR

Updated On:2018-04-23
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Interface Solution > DDR
> DDR IO > DDR1 - SSTL2 IO Library 
Cell Name Descriptions Type Process Gradation Literature
FOA0A_A33_TMVH33L25_
SSTL2C1WLVTTL_IO
UMC 0.18um GII Logic Process SSTL2 ClassI with 3.3V LVTTL combo IO Cell Library Library_Group 0.18um Silver
 
FOA0A_A33_TMVH33L25_
SSTL2C2WLVTTL_IO
UMC 0.18um GII Logic Process SSTL2 ClassII IO group with 3.3V LVTTL combo IO Cell Library Library_Group 0.18um Silver
FOA0A_O_TMVH33L25_SS
TL2C1WLVTTL_IO
UMC 0.18um GII Logic Process 2.5/3.3V SSTL2 ClassI/LVTTL combo IO with POC solution Library_Group 0.18um Silver
FOA0A_O_TMVH33L25_SS
TL2C2WLVTTL_IO
UMC 0.18um GII Logic Process 2.5V/3.3V SSTL2 Class II/LVTTL combo IO with POC solution Library_Group 0.18um Silver
FOC0H_A33_TMVH33L25_
SSTL2C1WLVTTL_IO
UMC 0.13um process,SSTL-2 (ClassI)/LVTTL (10mA) Combo I/O Cells; This IP is branched from 'FSC0H_D_TMVH33L25_SSTL2C1WLVTTL_IO'. Library_Group 0.13um Silver
FOC0H_A33_TMVH33L25_
SSTL2C2WLVTTL_IO
UMC 0.13um Logic Process,Specification for SSTL-2 Class-II and LVTTL Combo IO; This IP is branched from 'FSC0H_D_TMVH33L25_SSTL2C2WLVTTL_IO' Library_Group 0.13um Silver
FOC0H_B33_TMVH33VL25
V_SSTL2C1WLVTTL_IO
UMC 0.13um HS/FSG Logic Process Ultra-slim SSTL-2 (ClassI)/LVTTL (10mA) Combo I/O Cells Library_Group 0.13um Contact Sales
 
FOC0H_O33_TMVH33L25_
SSTL2C1WLVTT
UMC 0.13um HS/FSG SSTL2 (class 1) IO for BOAC Library_Group 0.13um Silver
FOC0H_O33_TMVH33L25_
SSTL2C2WLVTT
UMC 0.13um HS/FSG Logic Process 2.5V/3.3V SSTL2-Class II/LVTTL combo IO with POC solution Library_Group 0.13um Silver
FOC0H_P33_T25_SSTL2C
1_IO
UMC 0.13um HS/FSG Logic Process SSTL-2 (ClassI) mini BOAC I/O Cells Library_Group 0.13um Bronze
FOD0A_O25_T25_SSTL2C
1_IO
UMC 90nm SP/Low-K Logic Process SSTL-2 (ClassI) BOAC I/O Cells Library_Group 90nm Bronze
 
FOR0B_O33_TMVH25L18_
SSTL2WMDDR_IO
UMC 0.11um AE/HS Logic Process DD1/DDR2 combo MDDR IO Cell Library Library_Group 0.11um Bronze
FS90A_B_T25_SSTL2_IO UMC 0.25um LOGIC process true 2.5V SSTL-2 IO cells Library_Group 0.25um Silver
 
FS90A_B_TMVH33L25_SS
TL2C1WLVTTL_IO
UMC 0.25um process SSTL2 ClassI with 3.3V LVTTL combo. Library_Group 0.25um Silver
 
FSA0A_C_T25_SSTL2_IO UMC 0.18um GII process true 2.5V SSTL-2 IO cells Library_Group 0.18um Silver
FSA0A_C_TMVH33L25_SS
TL2C1WLVTTL_IO
UMC 0.18um process SSTL2 ClassI with 3.3V LVTTL combo Library_Group 0.18um Silver
FSA0A_C_TMVH33L25_SS
TL2C2WLVTTL_IO
UMC 0.18um process ,SSTL2 ClassII IO group with 3.3V LVTTL combo. Library_Group 0.18um Silver
FSB0G_A_TMVH33L25_SS
TL2C2WLVTTL_IO
UMC 0.15um SP process standard Multi-Voltage High 3.3V Low 2.5V SSTL-2 class-II with LVTTL IO cells. Library_Group 0.15um Silver