PowerSlash Core Cell Library

Updated On:2018-01-23
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Logic Libraries > PowerSlash Core Cell Library
> 9-Track > 9T HVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_BHS_POWERSLASH
_CORE
UMC 40nm LP/HVT Logic Process 9-Track Standard Cell Library (PowerSlash Core) Library_Group 40nm Silver
FSH0L_XHS_POWERSLASH
_CORE
UMC 40nm LP/HVT Logic Process SYNS-like 9T POWERSLASH Cell Library Library_Group 40nm Contact Sales
 
FSJ0C_CHS_POWERSLASH
_CORE
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35) Library_Group 28nm Bronze
FSJ0L_BHS_POWERSLASH
_CORE
UMC 28nm HLP/HVT Logic Process 9-track POWERSLASH_CORE core cell library Library_Group 28nm Silver
FSN0U_CHS_POWERSLASH
_CORE
UMC 22nm ULP/HVT Logic and Mixed-Mode Process 9-track Powerslash cell library enhanced for routing (C35) Library_Group 22nm Contact Sales
 
FSN0U_CRS_POWERSLASH
_CORE
UMC 22nm ULP/HVT Logic and Mixed-Mode Process 9-track POWERSLASH cell library enhanced for routing (C35) Library_Group 22nm Contact Sales