Clock

Updated On:2018-01-21
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Analog > Clock
> LC-PLL > 20M ~ 500M, LC-PLL 
Cell Name Descriptions Type Process Gradation Literature
FXLCPLL101HH0L Jitter clean integer-N LC-PLL for serdes, output frequency is 156.25M, input frequency is 25M for Low-Jitter Mode, 156.25M for Jitter-Clean Mode. UMC 40nm LP LowK Logic Process. Analog_IP 40nm Contact Sales
 
FXLCPLL101HJ0C Jitter clean integer-N LC-PLL for serdes, output frequency is 156.25M, input frequency 156.25M for Jitter-Clean Mode. UMC 28nm HPC Process. Analog_IP 28nm Contact Sales
FXLCPLL101HJ0P Jitter clean integer-N LC-PLL for serdes, output frequency is 156.25M, input frequency 156.25M for Jitter-Clean Mode. UMC 28nm HPC+ Process. Analog_IP 28nm Contact Sales