1-Port Register File

Updated On:2018-01-18
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM, Peri HVT, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSF0F_A_SYHVT UMC 55nm eFlash with peri HVT 1PRF Memory_IP 55nm Silver
FSF0F_L_SYHVT UMC 55nm eFlash One Port Register File with power-gating Memory_IP 55nm Silver
FSF0U_A_SYHVT UMC 55nm ULP Low-K process One Port Register File for periphery HVT Memory_IP 55nm Silver Minus
FSF0U_L_SYHVT UMC 55nm ULP process PG-One Port Register File for periphery HVT Memory_IP 55nm Silver Minus
FSF0U_W_SYHVT UMC 55nm uLP LowK Logic Process One Port Register File with well bias & periphery HVT Memory_IP 55nm Silver Minus
FSH0U_A_SYHVT UMC 40nm uLP Logic Process 1-Port Register File with Peri-HVT Memory_IP 40nm Contact Sales
 
FSJ0C_D_SYHVT UMC 28HPC 1PRF compiler with HVT peripheral Memory_IP 28nm Bronze
FSJ0C_L_SYHVT UMC 28nm HPC Logic process PG-One Port Register File with HVT Memory_IP 28nm Bronze