Clock

Updated On:2018-04-19
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Analog > Clock
> DLL > 20M ~ 500M, DLL 
Cell Name Descriptions Type Process Gradation Literature
FXDLL200HR0B 1.2V 50-200MHz DLL with programmable phase delay; UMC 0.11um HS/AE (AL Enhancement) Logic Process Analog_IP 0.11um Silver
FXDLL208HR0B DLL-based cell that generates 32 phase delay for FTSDC021; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process Analog_IP 0.11um Bronze
FXDLL330HR0H Input 100M~400MHz, Output 100M~400MHz DLL-based cell that generates two-channel DQS with 25% timing delay ; UMC 0.11um HS/RVT Logic Process Analog_IP 0.11um Bronze
FXDLL340HF0L UMC 55nm LP/RVT Low-K logic process, Operating frequency 80MHz-320MHz, DQS delay 6.25%-50%. Analog_IP 55nm Silver Minus
FXDLL340HH0L Input 80MHz-280MHz, DQS delay 6.25%-50% of FREF period, UMC 40nm LP/RVT Low-K logic process. Analog_IP 40nm Silver Minus
FXDLL340HJ0C DLL-based cell that generates 32 phase delay for SDIO; Frequency range: 52MHz~208MHz; UMC 28nm HPC Logic Process Analog_IP 28nm Contact Sales
FXDLL341HF0A Input 80MHz-280MHz, DQS delay 3.125%-50% of FREF period, UMC 55nm SP/RVT Low-K logic process. Analog_IP 55nm Silver Minus
FXDLL341HR0B 1.2V 50-202.5MHz DLL with programable phase delay; UMC 0.11um HS/AE (AL Enhancement) Logic Process Analog_IP 0.11um Contact Sales
 
FXDLL344HH0L Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process. Analog_IP 40nm Bronze
FXDLL360HD0A Input 18M-45M Hz, output 18M-45M Hz, timing generator DLL; UMC 90nm SP/RVT Lowk process Analog_IP 90nm Silver Minus
FXDLL365HD0A Input 5M-35M Hz, output 5M-35M Hz, timing generator DLL; UMC 90nm SP process Analog_IP 90nm Silver Minus