DDR

Updated On:2018-04-27
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Interface Solution > DDR
> DDR IO > DDR2 - SSTL18 IO Library 
Cell Name Descriptions Type Process Gradation Literature
FOC0H_O33_TMVH25L18_
SSTL18AWSSTL2C1_IO
UMC, 0.13um Logic HS/FSG process SSTL(2.5V) & SSTL18 (1.8V) combo IO Library_Group 0.13um Bronze
 
FOD0A_B25_T18_SSTL18
AWLVCMOS18_IO
UMC 90nm SP RVT process SSTL18 IO cell library Library_Group 90nm Contact Sales
 
FOF0L_PRS25_TMVH25L1
8_SSTL2WPWL_IO
55LP DDR1/DDR2 IO. 1. U55 LP Process 2. DDR2/DDR1 IO -2.5V SSTL2/1.8 SSTl18 ( CMOS/SSTL) –4 Driving strength @ Target: DDR 533 Mbps( IO 266 MHz) -VCCK Core power-off, All IO pull low Library_Group 55nm Bronze