DDR

Updated On:2018-04-23
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Interface Solution > DDR
 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3A50225EWHJ0L Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY Horizontal version; UMC 28nm HLP Logic and Mixed-Mode Process Analog_IP 28nm Contact Sales
FXDDR3A50225NSHJ0L Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY Vertical version; UMC 28nm HLP Logic and Mixed-Mode Process Analog_IP 28nm Contact Sales
FXDDR3D50225EWHJ0L Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY Horizontal version; UMC 28nm HLP Logic and Mixed-Mode Process Analog_IP 28nm Contact Sales
FXDDR3D50225NSHJ0L Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY Vertical version; UMC 28nm HLP Logic and Mixed-Mode Process Analog_IP 28nm Contact Sales
 
Interface Solution > DDR
> DDR Controller > DDR3 - Addresss/Command  
Cell Name Descriptions Type Process Gradation Literature
FXDDR3PHYA100EWHJ0C DDR3 RTL Digitalize PHY AC block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS Analog_IP 28nm Contact Sales
FXDDR3PHYA100NSHJ0C DDR3 RTL Digitalize PHY AC block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS Analog_IP 28nm Contact Sales
 
 
Interface Solution > DDR
> DDR Controller > DDR3 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3PHYD100EWHJ0C DDR3 RTL Digitalize PHY DATA block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS Analog_IP 28nm Contact Sales
 
FXDDR3PHYD100NSHJ0C DDR3 RTL Digitalize PHY DATA block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS Analog_IP 28nm Contact Sales
 
Interface Solution > DDR
> DDR IO > DDR3 - POD IO 
Cell Name Descriptions Type Process Gradation Literature
FOJ0L_QRS25_T15_DDR3
WPOD_IO
UMC 28nm HLP/RVT Low-K Logic process true 1.5V DDR3 with 2.5V Device IO cell Library Library_Group 28nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR3 PHY - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3AIO502EWHJ0C_F
TC
IO Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR ; UMC 28nm HPC/RVT Logic Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR4 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4AFD612EWHJ0C Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version ; UMC 28nm Logic and Mixed-Mode Low-K HPC Process Analog_IP 28nm Contact Sales
 
FXDDR4AFD612NSHJ0C Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version ; UMC 28nm Logic and Mixed-Mode Low-K HPC Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > LPDDR3 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4AFD612EWHJ0P Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version ; UMC 28nm Logic and Mixed-Mode Low-K HPC+ Process Analog_IP 28nm Contact Sales
 
FXDDR4AFD612NSHJ0P Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version ; UMC 28nm Logic and Mixed-Mode Low-K HPC+ Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Compensation > DDR3/3L - Compensation 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3COMP502HJ0C Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process Analog_IP 28nm Contact Sales
FXDDR3COMP502NSHJ0C Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process; Vertical version Analog_IP 28nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Compensation > LPDDR2 - Compensation 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3COMP50225EWHJ0
L
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 28nm HLP/RVT LowK Logic Process; Horizontal version Analog_IP 28nm Contact Sales
FXDDR3COMP50225NSHJ0
L
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 28nm HLP/RVT LowK Logic Process; Vertical version Analog_IP 28nm Contact Sales
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR3 PHY - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3DIO502NSHJ0C_F
TC
IO Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR ; UMC 28nm HPC/RVT Logic Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Data Block > LPDDR3 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4DFD612EWHJ0C Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 28nm Logic and Mixed-Mode Low-K HPC Process Analog_IP 28nm Contact Sales
 
FXDDR4DFD612EWHJ0P Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 28nm Logic and Mixed-Mode Low-K HPC+ Process Analog_IP 28nm Contact Sales
 
FXDDR4DFD612NSHJ0C Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 28nm Logic and Mixed-Mode Low-K HPC Process Analog_IP 28nm Contact Sales
 
FXDDR4DFD612NSHJ0P Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 28nm Logic and Mixed-Mode Low-K HPC+ Process Analog_IP 28nm Contact Sales