Analog

Updated On:2018-01-18
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Analog > A/D Converter
 
Cell Name Descriptions Type Process Gradation Literature
FXADC1502HJ0C 12 bit 1MSPS/200KSPS single-end SAR A/D Converter; UMC 28nm HPC process Analog_IP 28nm Contact Sales
 
 
Analog > A/D Converter
> Pipelined ADC > 9Bit Pipelined ADC 
Cell Name Descriptions Type Process Gradation Literature
FXADC210HJ0C 125M 9bit 2.5bit pipeline share-OP ADC; UMC 28nm HPC/Low-K process Analog_IP 28nm Silver Minus
FXADC210HJ0P 0.9V/1.8V 9Bits 125MSPS Pipelined ADC; UMC 28nm HPC+, LowK, Logic Process Analog_IP 28nm Contact Sales
 
 
Analog > A/D Converter
> SAR ADC > 10Bit SAR ADC 
Cell Name Descriptions Type Process Gradation Literature
FXADC1402HJ0C 10 bit 1MSPS SAR A/D Converter; UMC 28 nm HPC process Analog_IP 28nm Contact Sales
 
FXADC1403HJ0C 10 bit 1MSPS single-end SAR A/D Converter; UMC 28nm HPC process Analog_IP 28nm Contact Sales
 
FXADC150HJ0C 10 bit 1MSPS/200KSPS single-end SAR A/D Converter; UMC 28nm HPC process Analog_IP 28nm Bronze
FXADC151HJ0C 10 bit 1MSPS single-end SAR A/D Converter; UMC 28nm HPC process Analog_IP 28nm Bronze
 
Analog > Clock
> All Digital Delay Line > over 1G, All Digital Delay Line 
Cell Name Descriptions Type Process Gradation Literature
FXDCDL341HJ0C Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process Analog_IP 28nm Contact Sales
FXDCDL341HJ0G Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPM Process Analog_IP 28nm Bronze
FXDCDL342HJ0C Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 50% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process Analog_IP 28nm Contact Sales
FXDCDL342HJ0G Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 50% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPM Process Analog_IP 28nm Bronze
FXDCDL343HJ0C Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 25% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process Analog_IP 28nm Contact Sales
FXDCDL343HJ0G Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 25% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPM Process Analog_IP 28nm Bronze
 
Analog > Clock
> DLL > 20M ~ 500M, DLL 
Cell Name Descriptions Type Process Gradation Literature
FXDLL340HJ0C DLL-based cell that generates 32 phase delay for SDIO; Frequency range: 52MHz~208MHz; UMC 28nm HPC Logic Process Analog_IP 28nm Contact Sales
 
Analog > Clock
> Digitized DLL > 20M ~ 500M, Digitalized DLL 
Cell Name Descriptions Type Process Gradation Literature
FXADDLL310HJ0L Input 333M-800MHz, output 333M-800MHz, all digital DLL with one-channel DQS delay range ; UMC 28nm HLP Process Analog_IP 28nm Contact Sales
 
Analog > Clock
> Digitized DLL > over 1G, Digitalized DLL 
Cell Name Descriptions Type Process Gradation Literature
FXADDLL340HJ0C Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process. Analog_IP 28nm Contact Sales
FXADDLL340HJ0G Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPM Process Analog_IP 28nm Silver Minus
 
Analog > Clock
> LC-PLL > 20M ~ 500M, LC-PLL 
Cell Name Descriptions Type Process Gradation Literature
FXLCPLL101HJ0C Jitter clean integer-N LC-PLL for serdes, output frequency is 156.25M, input frequency 156.25M for Jitter-Clean Mode. UMC 28nm HPC Process. Analog_IP 28nm Contact Sales
FXLCPLL101HJ0P Jitter clean integer-N LC-PLL for serdes, output frequency is 156.25M, input frequency 156.25M for Jitter-Clean Mode. UMC 28nm HPC+ Process. Analog_IP 28nm Contact Sales
 
 
Analog > Clock
> Others 
Cell Name Descriptions Type Process Gradation Literature
FXCKTREE110NSHJ0C 200MHz, clock tree for CMC project; UMC 28nm HPC Analog_IP 28nm Contact Sales
 
 
Analog > Clock
> PLL > 20M ~ 500M, Generic PLL 
Cell Name Descriptions Type Process Gradation Literature
FXPLLHV362HJ0G Half low pass filter area compare with FXPLL362HJ0G, Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400MHz - 1600MHz, output,frequency synthesizable PLL;UMC 28nm HPM Logic Process Analog_IP 28nm Contact Sales
 
FXPLLLV362HJ0G This version has only one power domain and smaller PLL area than FXPLL362HJ0G, Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400MHz - 1600MHz, output,frequency synthesizable PLL;UMC 28nm HPM Logic Process Analog_IP 28nm Contact Sales
 
 
Analog > Clock
> PLL > 500M ~ 1G, Generic PLL 
Cell Name Descriptions Type Process Gradation Literature
FXPLL360HJ0G Input 25-66M Hz, output 400-800M Hz, frequency synthesizable PLL; UMC 28nm HPM Logic Process Analog_IP 28nm Silver Minus
FXPLL512HJ0C_DPHY Input 12M Hz, output 40M-850M Hz, frequency synthesizable PLL; UMC 28nm HPC Logic Process Analog_IP 28nm Bronze
 
Analog > Clock
> PLL > over 1G, Generic PLL 
Cell Name Descriptions Type Process Gradation Literature
FXPLL110HJ0C Input 10M-50M Hz, output 25M-1.3G Hz, frequency synthesizable PLL; UMC 28nm HPC Process Analog_IP 28nm Contact Sales
FXPLL110HJ0G Input 20M-200M Hz, output 62.5M-1G Hz, frequency synthesizable PLL; UMC 28nm Logic and Mixed-Mode HPM Process Analog_IP 28nm Contact Sales
 
FXPLL110HJ0L Input 20M-200M Hz, output 62.5M-1G Hz, frequency synthesizable PLL; UMC 28nm Logic and Mixed-Mode HLP Process Analog_IP 28nm Contact Sales
 
FXPLL225HJ0G Input 25M-50M Hz, output 1000M-2000MHz, frequency synthesizable PLL; UMC 28nm Logic and Mixed-Mode HPM Process Analog_IP 28nm Contact Sales
 
FXPLL357HJ0C Input 6~27MHz, output 160~3000MHz frequency synthesizable PLL; UMC 28HPC process Analog_IP 28nm Bronze
FXPLL362HJ0C Input 200MHz~400MHz, output 200MHz~1600MHz frequency synthesizable PLL; UMC 28nm HPC Logic Process Analog_IP 28nm Contact Sales
FXPLL530HJ0C Input 6~27MHz, Output 62.5~2000MHz PLL, UMC 28nm HPC process. Analog_IP 28nm Contact Sales
 
Analog > Clock
> SSCG > 500M ~ 1G, SSCG 
Cell Name Descriptions Type Process Gradation Literature
FXSSCG360HJ0C Input 25~66MHz, output 200~800MHz wide range SSCG PLL, UMC 28nm HPC/RVT process. Analog_IP 28nm Bronze
 
Analog > Codecs ADDA
> SigmaDelta ADDA > 24Bit High Performance Stereo Audio CODEC 
Cell Name Descriptions Type Process Gradation Literature
FXADDA302HJ0C UMC 28nm high performance stereo audio codec with highly integrated analog functionality system Analog_IP 28nm Contact Sales
 
Analog > D/A Converter
> Video DAC > 10Bit 3-Channel Video DAC 
Cell Name Descriptions Type Process Gradation Literature
FXDAC030HJ0C 10bit 150MSPS 3-ch Video DAC,UMC 28nm HPC process Analog_IP 28nm Bronze
 
Analog > Data Converter
> TDC Converter 
Cell Name Descriptions Type Process Gradation Literature
FXTDC010HJ0C A 10bit 1ksps temperature to digital converter ; UMC 28nm HPC/RVT Logic and Mixed-mode Process Analog_IP 28nm Bronze
FXTDC011HJ0C A 10bit 1ksps temperature to digital converter ; UMC 28nm HPC/RVT Logic and Mixed-mode Process Analog_IP 28nm Contact Sales
FXTDC030HJ0C A 10bit 1ksps temperature to digital converter ; UMC 28nm HPC/RVT Logic and Mixed-mode Process Analog_IP 28nm Contact Sales
 
 
Analog > Power
> Band Gap 
Cell Name Descriptions Type Process Gradation Literature
FXBG020HJ0C Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC Process Analog_IP 28nm Silver Minus
FXBG020HJ0L Input 0.945V-1.155V, VBG=0.8V,Band Gap; UMC 28m HLP Process Analog_IP 28nm Bronze
FXBG020HJ0P Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC+ Process Analog_IP 28nm Contact Sales
FXBG021HJ0C Power input 1.8v, VBG=0.75V Band-gap, UMC 28nm HPC Logic process Analog_IP 28nm Contact Sales
 
Analog > Power
> Linear Regulator 
Cell Name Descriptions Type Process Gradation Literature
FXREG010HJ0C 3.3V to 1.8V/150mA REG with external Capacitor, UMC 28nm HPC Logic and Mixed-Mode Process Analog_IP 28nm Bronze
FXREG011HJ0C 3.3V to 1.8V/50mA REG with external Capacitor, UMC 28nm HPC Logic and Mixed-Mode Process Analog_IP 28nm Bronze
FXREG012HJ0C 3.3V to 1.8V/50mA REG with external Capacitor, UMC 28nm HPC Logic and Mixed-Mode Process Analog_IP 28nm Contact Sales
FXREG014HJ0C 3.3V to 1.8V with 50mA driving capability; Capacitor-free Linear Regulator; UMC 28nm HPC Process Analog_IP 28nm Bronze
FXREG020HJ0C 3.3V to 0.9V/150mA REG, Linear Regulator, UMC 28nm HPC Logic and Mixed-Mode Process Analog_IP 28nm Bronze
FXREG024HJ0C 3.3V to 0.9V with 50mA driving capability; Capacitor-free Linear Regulator; UMC 28nm HPC Process Analog_IP 28nm Contact Sales
FXREG030HJ0C 1.8V to 0.9V with 300mA driving capability; Capacitor Linear Regulator; UMC 28nm HPC Process Analog_IP 28nm Contact Sales
 
FXREG110HJ0C 3.3V to 1.8V with 10uA driving capability; Capacitor-free Linear Regulator; UMC 28nm HPC Process Analog_IP 28nm Contact Sales
FXREG111HJ0C 3.3v to 1.2v/1ma with power switch function ,UMC 28nm HPC Logic process Analog_IP 28nm Contact Sales
FXREG112HJ0C 3.3V to 0.9V with 2mA driving capability,Linear Regulator; UMC 28nm HPC Logic and Mixed-Mode process Analog_IP 28nm Contact Sales
 
FXREG210HJ0C 3.3V to 2.0V with 288mA driving capability with external capacitor,use trimming ports (need e-Fuse IP); Linear Regulator; UMC 28nm Logic HPC Process Analog_IP 28nm Contact Sales
FXREG300HJ0C 3.3V to 2.5V with 5mA driving capability; Capacitor-free Linear Regulator; UMC 28nm HPC Process Analog_IP 28nm Silver Minus
FXREG320HJ0C Source and Sink Current 100mA LDO for 28nm cascade I/O, UMC 28nm HPC Logic and Mixed-Mode Process Analog_IP 28nm Contact Sales
 
FXRGSO010HJ0C Source Low Dropout Linear Regulator for Cascade IO ; UMC 28nm HPC Process Analog_IP 28nm Contact Sales
 
 
Analog > Power
> Power on Reset 
Cell Name Descriptions Type Process Gradation Literature
FXPORALH230HJ0CEW Input VCC18V=1.8V, 1.8V Power On Reset for East-West Orientation; UMC 28nm HPC Logic Process Analog_IP 28nm Bronze
FXPORALH230HJ0CNS Input VCC18V=1.8V, 1.8V Power On Reset for North-South Orientation; UMC 28nm HPC Logic Process Analog_IP 28nm Contact Sales
 
FXPORK600HJ0C Input VCC=0.9V, 0.9V Power On Reset without Vfr; UMC 28nm HPC Logic Process Analog_IP 28nm Bronze
FXPORK630HJ0C Vrr=0.63V,Vfr=0.56V,input VCC=0.9V, 0.9V Power On Reset; UMC 28nm HPC Logic Process Analog_IP 28nm Bronze
FXPORKHR230HJ0C 1.8V RTC Power-On-Reset, UMC 28nm HPC Process Analog_IP 28nm Bronze
FXPORKLH230HJ0C Input VCC18V=1.8V, 1.8V Power On Reset; UMC 28nm HPC Logic Process Analog_IP 28nm Bronze
 
Analog > Power
> Voltage Detector 
Cell Name Descriptions Type Process Gradation Literature
FXVDT021HJ0C 4-Level Voltage Detector for USB-OTG ; UMC 28nm HPC Process Analog_IP 28nm Silver Minus
FXVDT022HJ0C Power input 3.3v or 1.8v, 2-set voltage detector, UMC 28nm HPC Logic Process Analog_IP 28nm Contact Sales
FXVDT023HJ0C Power input 1.8v, Detect level 0.7V~1.8V and 2.5V~2.9V, 2-set voltage detector, UMC 28nm HPC Logic Process Analog_IP 28nm Contact Sales