Clock

Updated On:2018-04-21
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Analog > Clock
> All Digital Delay Line > over 1G, All Digital Delay Line 
Cell Name Descriptions Type Process Gradation Literature
FXDCDL341HJ0C Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process Analog_IP 28nm Contact Sales
FXDCDL341HJ0P Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0P to generate 100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC + Process Analog_IP 28nm Contact Sales
 
FXDCDL342HJ0C Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 50% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process Analog_IP 28nm Contact Sales
FXDCDL342HJ0P Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0P to generate 50% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC + Process Analog_IP 28nm Contact Sales
 
FXDCDL343HJ0C Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 25% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process Analog_IP 28nm Contact Sales
FXDCDL343HJ0P Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0P to generate 25% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC + Process Analog_IP 28nm Contact Sales
 
 
Analog > Clock
> DLL > 20M ~ 500M, DLL 
Cell Name Descriptions Type Process Gradation Literature
FXDLL340HJ0C DLL-based cell that generates 32 phase delay for SDIO; Frequency range: 52MHz~208MHz; UMC 28nm HPC Logic Process Analog_IP 28nm Contact Sales
 
Analog > Clock
> Digitized DLL > 20M ~ 500M, Digitalized DLL 
Cell Name Descriptions Type Process Gradation Literature
FXADDLL310HJ0L Input 333M-800MHz, output 333M-800MHz, all digital DLL with one-channel DQS delay range ; UMC 28nm HLP Process Analog_IP 28nm Contact Sales
 
Analog > Clock
> Digitized DLL > over 1G, Digitalized DLL 
Cell Name Descriptions Type Process Gradation Literature
FXADDLL340HJ0C Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process. Analog_IP 28nm Contact Sales
FXADDLL340HJ0P Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 28nm HPC+ Logic and Mixed-Mode Process. Analog_IP 28nm Contact Sales
 
 
Analog > Clock
> LC-PLL > 20M ~ 500M, LC-PLL 
Cell Name Descriptions Type Process Gradation Literature
FXLCPLL101HJ0C Jitter clean integer-N LC-PLL for serdes, output frequency is 156.25M, input frequency 156.25M for Jitter-Clean Mode. UMC 28nm HPC Process. Analog_IP 28nm Contact Sales
FXLCPLL101HJ0P Jitter clean integer-N LC-PLL for serdes, output frequency is 156.25M, input frequency 156.25M for Jitter-Clean Mode. UMC 28nm HPC+ Process. Analog_IP 28nm Contact Sales
 
 
Analog > Clock
> Others 
Cell Name Descriptions Type Process Gradation Literature
FXCKTREE110NSHJ0C 200MHz, clock tree for CMC project; UMC 28nm HPC Analog_IP 28nm Contact Sales
 
 
Analog > Clock
> PLL > 500M ~ 1G, Generic PLL 
Cell Name Descriptions Type Process Gradation Literature
FXPLL360HJ0G Input 25-66M Hz, output 400-800M Hz, frequency synthesizable PLL; UMC 28nm HPM Logic Process Analog_IP 28nm Silver Minus
FXPLL512HJ0C_DPHY Input 12M Hz, output 40M-850M Hz, frequency synthesizable PLL; UMC 28nm HPC Logic Process Analog_IP 28nm Bronze
 
Analog > Clock
> PLL > over 1G, Generic PLL 
Cell Name Descriptions Type Process Gradation Literature
FXPLL110HJ0C Input 10M-50M Hz, output 25M-1.3G Hz, frequency synthesizable PLL; UMC 28nm HPC Process Analog_IP 28nm Contact Sales
FXPLL110HJ0L Input 20M-200M Hz, output 62.5M-1G Hz, frequency synthesizable PLL; UMC 28nm Logic and Mixed-Mode HLP Process Analog_IP 28nm Contact Sales
 
FXPLL357HJ0C Input 6~27MHz, output 160~3000MHz frequency synthesizable PLL; UMC 28HPC process Analog_IP 28nm Bronze
FXPLL362HJ0C Input 200MHz~400MHz, output 200MHz~1600MHz frequency synthesizable PLL; UMC 28nm HPC Logic Process Analog_IP 28nm Contact Sales
FXPLL362HJ0P Input 200MHz~400MHz, output 200MHz~1600MHz frequency synthesizable PLL; UMC 28nm HPC+ Logic and Mixed-Mode Process Analog_IP 28nm Contact Sales
 
FXPLL530HJ0C Input 6~27MHz, Output 62.5~2000MHz PLL, UMC 28nm HPC process. Analog_IP 28nm Contact Sales
 
Analog > Clock
> SSCG > 500M ~ 1G, SSCG 
Cell Name Descriptions Type Process Gradation Literature
FXSSCG360HJ0C Input 25~66MHz, output 200~800MHz wide range SSCG PLL, UMC 28nm HPC/RVT process. Analog_IP 28nm Bronze
FXSSCG360HJ0P Input 24~66MHz, output 200~800MHz wide range SSCG PLL, UMC 28nm HPC+ process. Analog_IP 28nm Contact Sales