Memory Compiler

Updated On:2018-06-21
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0P_D_SYHVT UMC 28HPC+ 1PRF compiler with HVT peripheral Memory_IP 28nm Contact Sales
 
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_B_SY UMC 28nm HPC process One Port Register File Memory_IP 28nm Silver Minus
FSJ0C_D_SY UMC 28nm HPC Logic Process Ultra High Density 1-Port Register File Memory Compiler Memory_IP 28nm Silver Minus
FSJ0L_B_SY UMC 28nm HLP/Low-k One Port Register File Memory_IP 28nm Silver Minus
 
FSJ0P_D_SY UMC 28nm HPC Plus Process Standard Synchronous High Density Single Port Register File Memory Compiler. Memory_IP 28nm Contact Sales
 
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM, Peri HVT, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_D_SYHVT UMC 28HPC 1PRF compiler with HVT peripheral Memory_IP 28nm Bronze
FSJ0C_L_SYHVT UMC 28nm HPC Logic process PG-One Port Register File with HVT Memory_IP 28nm Bronze
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_B_SYLVT UMC 28nm HPC process One Port Register File with LVT Memory_IP 28nm Bronze
 
FSJ0C_D_SYLVT UMC 28HPC process 1PRF compiler with LVT peripheral Memory_IP 28nm Bronze
FSJ0L_B_SYLVT UMC 28nm HLP Logic Process One Port Register File with LVT Memory_IP 28nm Bronze
 
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM, Peri LVT, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_L_SYLVT UMC 28nm HPC Logic process PG One Port Register File with LVT Memory_IP 28nm Bronze
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_L_SY UMC 28nm HPC Logic process PG One Port Register File Memory_IP 28nm Silver Minus
 
Memory Compiler > 1-Port Register File
> 6TSRAM > Ultra High Speed 1PRF, 6TSRAM  
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_A_SQ UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler Memory_IP 28nm Bronze
FSJ0L_A_SQ UMC 28nm Logic process standard synchronous Ultra High Speed Single Port Register File SRAM memory compiler. Memory_IP 28nm Bronze
 
Memory Compiler > 1-Port Register File
> 6TSRAM > Ultra High Speed 1PRF, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_A_SQLVT UMC 28nm HPC Process Ultra High Speed One Port Register File Memory Compiler with periphery LVT Memory_IP 28nm Silver Minus
FSJ0C_L_SELVT Synchronous LVT Periphery Ultra-High-Speed Single-Port SRAM Compiler Memory_IP 28nm Bronze
FSJ0L_A_SQLVT UMC 28nm HLP/UHS 1PRF compiler with peri LVT Memory_IP 28nm Bronze
 
Memory Compiler > 1-Port Register File
> 6TSRAM > Ultra High Speed 1PRF, 6TSRAM, Peri LVT/RVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0P_A_SQHVT UMC 28nm Logic and Mixed-Mode High Performance Process Synchronous HVT+RVT Periphery Ultra-High-Speed One-Port Register File Compiler Memory_IP 28nm Contact Sales
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density & Low Power 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_L_SH UMC 28nm HPC Logic Process PG Single Port SRAM memory compiler Memory_IP 28nm Silver Minus
FSJ0C_L_SHR1 UMC 28nm HPC process standard synchronous high density single port low power SRAM memory compiler with row redundancy Memory_IP 28nm Bronze
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density & Low Power 1PSRAM, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_L_SHHVT UMC 28nm HPC Logic Process PG Single-Port SRAM with HVT memory compiler Memory_IP 28nm Bronze
FSJ0C_L_SHHVTR1 UMC 28nm HPC process standard synchronous HVT periphery high density single port low power SRAM memory compiler with row redundancy Memory_IP 28nm Bronze
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density & Low Power 1PSRAM, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_L_SHLVT UMC 28nm HPC Logic Process PG Single Port SRAM with LVT memory compiler Memory_IP 28nm Bronze
FSJ0C_L_SHLVTR1 UMC 28nm HPC process standard synchronous LVT periphery high density single port low power SRAM memory compiler with row redundancy Memory_IP 28nm Bronze
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_B_SH UMC 28nm Logic process standard synchronous RVT periphery high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0C_B_SHR1 UMC 28nm Logic process standard synchronous RVT periphery high density single port SRAM memory compiler with row redundancy. Memory_IP 28nm Bronze
FSJ0C_D_SH UMC 28nm HPC Logic Process Ultra High Density Single-Port SRAM Memory Compiler Memory_IP 28nm Silver Minus
FSJ0G_B_SH UMC 28nm HPM process standard synchronous high density single port SRAM memory compiler Memory_IP 28nm Silver Minus
FSJ0L_B_SH High Density Single Port SRAM, UMC 28nm HLP process Memory_IP 28nm Silver Minus
FSJ0L_B_SHC1 UMC 28nm HLP process standard synchronous high density single port SRAM memory compiler. Memory_IP 28nm Contact Sales
 
FSJ0L_B_SHR1 UMC 28nm HLP standard synchronous high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0L_B_SHR1C1 UMC 28nm HLP process standard synchronous High density single port SRAM memory compiler. Memory_IP 28nm Contact Sales
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM, Peri H/RVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_D_SHHVTR1 UMC 28nm HPC Process Synchronous HVT/RVT Periphery High Density Single Port SRAM Memory Compiler with Row Redundancy Memory_IP 28nm Bronze
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_D_SHHVT UMC 28nm HPC process synchronous HVT periphery high density single port SRAM memory compiler. Memory_IP 28nm Silver Minus
FSJ0P_D_SHHVT UMC 28HPC+ UHD SPSRAM compiler Memory_IP 28nm Contact Sales
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_B_SHLVT UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler. Memory_IP 28nm Silver Minus
FSJ0C_B_SHLVTR1 UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0C_D_SHLVT UMC 28nm HPC process synchronous LVT periphery high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0C_D_SHLVTR1 UMC 28nm HPC Process Synchronous LVT/RVT Periphery High Density Single Port SRAM Memory Compiler with Row Redundancy Memory_IP 28nm Contact Sales
FSJ0L_B_SHLVT UMC 28nm HLP Logic process LVT standard synchronous high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0L_B_SHLVTC1 UMC 28nm HLP process standard LVT synchronous high density single port SRAM memory compiler. Memory_IP 28nm Contact Sales
 
FSJ0L_B_SHLVTR1 UMC 28nm HLP Logic process LVT standard synchronous high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0L_B_SHLVTR1C1 UMC 28nm HLP process LVT standard synchronous high density single port SRAM memory compiler. Memory_IP 28nm Contact Sales
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > Ultra High Density 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_D_SHR1 UMC 28nm HPC Logic Process Ultra High Density Single-Port SRAM Memory Compiler with Row Redundancy Memory_IP 28nm Contact Sales
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > Ultra High Speed 1PSRAM, 6T SRAM 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_A_SE UMC 28nm HPC Process Ultra High Speed Single-Port SRAM memory compiler Memory_IP 28nm Bronze
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > Ultra High Speed 1PSRAM, 6T SRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_A_SELVT UMC 28nm HPC Process Ultra High Speed Single-Port SRAM Memory Compiler Memory_IP 28nm Silver Minus
 
Memory Compiler > 2-Port Register File
> 6TSRAM > High Density and Ultra Low Power 2PRF, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0P_L_SZHVT 28nm HPC+ logic process 2PRF with NAP/RET/SLP modes memory compiler Memory_IP 28nm Contact Sales
 
 
Memory Compiler > 2-Port Register File
> 8TSRAM > High Density 2PRF, 8TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_A_SZ UMC 28nm HPC process Two Port Register File Memory_IP 28nm Silver Minus
FSJ0C_A_SZB2 UMC 28nm HPC process 2PRF with Bank2 Memory_IP 28nm Contact Sales
 
FSJ0C_A_SZB4 UMC 28nm HPC process Two Port Register File with Bank2 Memory_IP 28nm Bronze
FSJ0L_A_SZ UMC 28nm HLP/Low-K 2PRF compiler Memory_IP 28nm Silver Minus
 
Memory Compiler > 2-Port Register File
> 8TSRAM > High Density 2PRF, 8TSRAM, Peri HVT, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_L_SZHVT UMC 28nm HPC process PG Two Port Register File with peri-HVT Memory_IP 28nm Bronze
FSJ0C_L_SZHVTB2 UMC 28nm HPC process 2PRF, HVT & Bank2 Memory_IP 28nm Bronze
FSJ0C_L_SZHVTB4 UMC 28nm HPC process PG-2PRF with HVT Bank4 Memory_IP 28nm Bronze
 
Memory Compiler > 2-Port Register File
> 8TSRAM > High Density 2PRF, 8TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_A_SZLVT UMC 28nm HPC process Two Port Register File with peri LVT Memory_IP 28nm Silver Minus
FSJ0C_A_SZLVTB2 UMC 28nm HPC process Two Port Register File with LVT and Bank2 Memory_IP 28nm Bronze
FSJ0C_A_SZLVTB4 UMC 28nm HPC process Two Port Register File with LVT and Bank4 Memory_IP 28nm Bronze
FSJ0L_A_SZLVT 28HLP periphery LVT Two Port Register File Memory Compiler Memory_IP 28nm Bronze
 
Memory Compiler > 2-Port Register File
> 8TSRAM > High Density 2PRF, 8TSRAM, Peri LVT, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_L_SZLVT UMC 28nm HPC process PG Two Port Register File with peri-LVT Memory_IP 28nm Bronze
FSJ0C_L_SZLVTB2 UMC 28nm HPC process 2PRF with LVT and Bank 2 Memory_IP 28nm Bronze
FSJ0C_L_SZLVTB4 UMC 28nm HPC process PG-2PRF with LVT and Bank 2 Memory_IP 28nm Bronze
 
Memory Compiler > 2-Port Register File
> 8TSRAM > High Density 2PRF, 8TSRAM, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_L_SZ UMC 28nm HPC process PG Two Port Register File Memory_IP 28nm Silver Minus
FSJ0C_L_SZB2 UMC 28nm HPC process 2PRF with Bank2 & power gating Memory_IP 28nm Bronze
 
FSJ0C_L_SZB4 UMC 28nm HPC process PG-2PRF with Bank4 Memory_IP 28nm Bronze
 
Memory Compiler > 2-Port SRAM
> 8TSRAM > Synchronous High Density 2PSRAM, 8TSRAM peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_A_SZHVTB4 UMC 28HPC Process Standard Synchronous High Density Two Port SRAM Memory Compiler. Memory_IP 28nm Bronze
 
Memory Compiler > Dual-Port SRAM
> 6TSRAM > High Density DPSRAM, 6TSRAM, Peri LVT, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_L_SJLVT UMC 28nm HPC process PG-Dual Port SRAM with LVT Memory_IP 28nm Bronze
FSJ0C_L_SJLVTR1 UMC 28nm HPC process PG Dual Port SRAM with LVT Memory_IP 28nm Bronze
 
 
Memory Compiler > Dual-Port SRAM
> 6TSRAM > High Density DPSRAM, 6TSRAM, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_L_SJ UMC 28nm HPC process Dual Port SRAM with Power gating Memory_IP 28nm Bronze
FSJ0C_L_SJR1 UMC 28nm HPC Process dual port SRAM with power gating Memory_IP 28nm Bronze
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_A_SJ UMC 28nm HPC process Dual Port SRAM compiler Memory_IP 28nm Bronze
FSJ0C_A_SJR1 UMC 28nm HPC process Dual Port SRAM with row reapir Memory_IP 28nm Bronze
FSJ0C_L_SJHVT UMC 28nm HPC process standard synchronous high density dual port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0L_A_SJ UMC 28nm HLP/Low-k Dual-Port SRAM compiler Memory_IP 28nm Contact Sales
 
FSJ0L_A_SJR1 UMC 28nm HLP Logic Process ; Dual Port SRAM compiler with R1 Memory_IP 28nm Contact Sales
 
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_A_SJHVT UMC 28nm HPC process Dual Port SRAM compiler Memory_IP 28nm Bronze
FSJ0C_A_SJHVTR1 UMC 28nm HPC process Dual Port SRAM compiler Memory_IP 28nm Bronze
FSJ0C_L_SJHVTR1 UMC 28HPC process standard synchronous high density dual port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0P_A_SJHVT UMC 28nm HPC+ process dual port SRAM memory compiler with HVT+RVT peripheral Memory_IP 28nm Contact Sales
 
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_A_SJLVT UMC 28nm HPC process Dual Port SRAM with LVT Memory_IP 28nm Bronze
FSJ0C_A_SJLVTR1 UMC 28nm HPC process Dual Port SRAM with row repair & LVT Memory_IP 28nm Bronze
FSJ0L_A_SJLVT UMC 28nm HLP Logic Process ; Dual Port SRAM compiler with LVT Memory_IP 28nm Contact Sales
 
 
Memory Compiler > ROM
> Contact ROM > Contact ROM, Peri RVT/HVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_B_SPHVT UMC 28HPC RVT/HVT Logic Process Standard Synchronous Contact ROM memory Compiler. Memory_IP 28nm Bronze
 
 
Memory Compiler > ROM
> Contact ROM > Contact ROM, Peri RVT/LVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_B_SPLVT UMC 28HPC LVT/RVT Logic Process Standard Synchronous Contact ROM memory Compiler. Memory_IP 28nm Bronze
 
Memory Compiler > ROM
> VIA1 ROM > VIA1 ROM 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_B_SP 28HPC Process Standard Synchronous Feature ROM Memory Compiler. Memory_IP 28nm Bronze
FSJ0C_L_SP UMC 28nm HPC Process PG Via ROM Compiler Memory_IP 28nm Silver Minus
FSJ0L_A_SP UMC 28nm HLP/Low-K Via ROM compiler Memory_IP 28nm Contact Sales
 
 
Memory Compiler > ROM
> VIA1 ROM > VIA1 ROM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_L_SPHVT UMC 28nm HPC Logic Process Via ROM Low Power Compiler with HVT peripheral Memory_IP 28nm Bronze
FSJ0P_A_SPHVT UMC 28nm logic-mixed MODE28N-HPCUP synchronous Contact ROM memory compiler. Memory_IP 28nm Contact Sales
 
 
Memory Compiler > ROM
> VIA1 ROM > VIA1 ROM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_L_SPLVT UMC 28nm HLC Logic process PG-Via1 ROM Compiler with LVT Memory_IP 28nm Bronze
 
Memory Compiler > TCAM SRAM
> High Density TCAM 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_A_SFLVT UMC 28HPC process standard synchronous high density TCAM memory compiler Memory_IP 28nm Silver Minus