Interface Solution

Updated On:2018-01-24
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Interface Solution > DDR
 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3A50225EWHJ0L Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY Horizontal version; UMC 28nm HLP Logic and Mixed-Mode Process Analog_IP 28nm Contact Sales
 
FXDDR3A50225NSHJ0L Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY Vertical version; UMC 28nm HLP Logic and Mixed-Mode Process Analog_IP 28nm Contact Sales
 
FXDDR3D50225EWHJ0L Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY Horizontal version; UMC 28nm HLP Logic and Mixed-Mode Process Analog_IP 28nm Contact Sales
 
FXDDR3D50225NSHJ0L Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY Vertical version; UMC 28nm HLP Logic and Mixed-Mode Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > DDR
> DDR Controller > DDR3 - Addresss/Command  
Cell Name Descriptions Type Process Gradation Literature
FXDDR3PHYA100EWHJ0C DDR3 RTL Digitalize PHY AC block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS Analog_IP 28nm Contact Sales
 
Interface Solution > DDR
> DDR Controller > DDR3 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3PHYD100NSHJ0C DDR3 RTL Digitalize PHY DATA block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS Analog_IP 28nm Contact Sales
 
Interface Solution > DDR
> DDR IO > DDR3 - POD IO 
Cell Name Descriptions Type Process Gradation Literature
FOJ0L_QRS25_T15_DDR3
WPOD_IO
UMC 28nm HLP/RVT Low-K Logic process true 1.5V DDR3 with 2.5V Device IO cell Library Library_Group 28nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR3 PHY - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3AIO502EWHJ0C_F
TC
IO Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR ; UMC 28nm HPC/RVT Logic Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR4 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4AFD612EWHJ0C Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version ; UMC 28nm Logic and Mixed-Mode Low-K HPC Process Analog_IP 28nm Contact Sales
 
FXDDR4AFD612NSHJ0C Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version ; UMC 28nm Logic and Mixed-Mode Low-K HPC Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > LPDDR3 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4AFD612EWHJ0P Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version ; UMC 28nm Logic and Mixed-Mode Low-K HPC+ Process Analog_IP 28nm Contact Sales
 
FXDDR4AFD612NSHJ0P Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version ; UMC 28nm Logic and Mixed-Mode Low-K HPC+ Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Compensation > DDR3/3L - Compensation 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3COMP502HJ0C Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process Analog_IP 28nm Contact Sales
FXDDR3COMP502NSHJ0C Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process; Vertical version Analog_IP 28nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Compensation > LPDDR2 - Compensation 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3COMP50225EWHJ0
L
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 28nm HLP/RVT LowK Logic Process; Horizontal version Analog_IP 28nm Contact Sales
 
FXDDR3COMP50225NSHJ0
L
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 28nm HLP/RVT LowK Logic Process; Vertical version Analog_IP 28nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR3 PHY - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3DIO502NSHJ0C_F
TC
IO Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR ; UMC 28nm HPC/RVT Logic Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Data Block > LPDDR3 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4DFD612EWHJ0C Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 28nm Logic and Mixed-Mode Low-K HPC Process Analog_IP 28nm Contact Sales
 
FXDDR4DFD612EWHJ0P Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 28nm Logic and Mixed-Mode Low-K HPC+ Process Analog_IP 28nm Contact Sales
 
FXDDR4DFD612NSHJ0C Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 28nm Logic and Mixed-Mode Low-K HPC Process Analog_IP 28nm Contact Sales
 
FXDDR4DFD612NSHJ0P Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 28nm Logic and Mixed-Mode Low-K HPC+ Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > Ethernet
> Ethernet PHY > 10/100 TX Ethernet PHY 
Cell Name Descriptions Type Process Gradation Literature
FXEDP110HJ0C 10BASE-T/100BASE-TX/100BASE-FX Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process Analog_IP 28nm Contact Sales
 
FXEDP310EWHJ0L FXEDP310HJ0L, 10BASE-T/100BASE-TX/100BASE-FX Energy Efficient Ethernet PHY; UMC 28nm HLP process Analog_IP 28nm Contact Sales
 
 
Interface Solution > Ethernet
> Ethernet PHY > 10/100/1000 TX Ethernet PHY 
Cell Name Descriptions Type Process Gradation Literature
FXEDP210HJ0C 10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process Analog_IP 28nm Contact Sales
FXEDP210HJ0P 10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC+/LOW_K process Analog_IP 28nm Contact Sales
 
 
Interface Solution > LVDS
> FPD LVDS Receiver 
Cell Name Descriptions Type Process Gradation Literature
FXLVRX020HJ0C LVDS RX Receives serial LVDS signal and de-serialize them into parallel format ; UMC 28nm HPC Logic Process Analog_IP 28nm Contact Sales
FXLVRX020HJ0P UMC 28nm HPC+ Logic Process, LVDS RX Receives serial LVDS signal and de-serialize them into parallel format Analog_IP 28nm Contact Sales
 
 
Interface Solution > LVDS
> FPD LVDS Transmitter 
Cell Name Descriptions Type Process Gradation Literature
FXLVTX020HJ0C 3.3V FPD-link LVDS Transmitter 16~100MHz; UMC 28nm HPC process Analog_IP 28nm Contact Sales
FXLVTX020HJ0P 3.3V FPD-link LVDS Transmitter 16~100MHz; UMC 28nm HPC plus proces Analog_IP 28nm Contact Sales
 
FXLVTX030HJ0C LVDS Transmitter 700Mbps; UMC 28nm HPC Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > LVDS
> IO LVDS Receiver 
Cell Name Descriptions Type Process Gradation Literature
FXLVIORX1105EWHJ0C 28nm HPC, LVDS RXIO, 500Mbps, 1.8V/0.9V Analog_IP 28nm Contact Sales
FXLVIORX1105NSHJ0C 28nm HPC, LVDS RXIO, 500Mbps, 1.8V/0.9V Analog_IP 28nm Contact Sales
 
 
Interface Solution > LVDS
> Sub-LVDS Receiver 
Cell Name Descriptions Type Process Gradation Literature
FXSLVRX112HJ0C 1.8V Sub-LVDS Receiver 650Mbps; UMC 28nm HPC process Analog_IP 28nm Contact Sales
 
 
Interface Solution > MIPI
 
Cell Name Descriptions Type Process Gradation Literature
FXDPHYTX8111HJ0C MIPI Transmitter 80Mbps~1.5Gbps without LP-mode ; UMC 28nm HPC Logic and Mixed-Mode Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > MIPI
> MIPI CPHY > MIPI CPHY Receiver 
Cell Name Descriptions Type Process Gradation Literature
FXCDPHYRX3401HJ0C MIPI Receiver CPHY 80Msps~2.5Gsps; DPHY 80Mbps~2.5Gbps ; UMC 28nm HPC process Analog_IP 28nm Contact Sales
 
 
Interface Solution > MIPI
> MIPI CPHY > MIPI CPHY Transmitter 
Cell Name Descriptions Type Process Gradation Literature
FXCDPHYTX3401HJ0C MIPI Transmitter CPHY 80Msps~2.5Gsps; DPHY 80Mbps~2.5Gbps ; UMC 28nm HPC process Analog_IP 28nm Contact Sales
 
 
Interface Solution > MIPI
> MIPI DPHY > MIPI DPHY Receiver 
Cell Name Descriptions Type Process Gradation Literature
FXDPHYRX12112HJ0C MIPI DPHY Reciever 80Mbps~2.5Gbps ; UMC 28nm HPC Logic Process Analog_IP 28nm Contact Sales
 
FXDPHYRX12112HJ0P MIPI DPHY Reciever 80Mbps~2.5Gbps ; UMC 28nm HPC+ Process Analog_IP 28nm Contact Sales
 
FXDPHYRX4111HJ0C MIPI Receiver, DPHY V1.1 RX ; UMC 28nm HPC process Analog_IP 28nm Contact Sales
 
FXDPHYRX4112HJ0C MIPI Receiver, DPHY V1.2 RX ; UMC 28nm HPC process Analog_IP 28nm Bronze
FXDPHYRX4112HJ0P MIPI RX 80Mbps~2.5Gbps ; UMC 28nm HPC+ process Analog_IP 28nm Contact Sales
 
FXDPHYRX4212HJ0C MIPI CSI Receiver 1G/ SLVDS 1G /HiSPi 1G, 1.8V/3.3V GPI 100MHz; UMC 28nm HPC Logic Process Analog_IP 28nm Contact Sales
 
FXDPHYRX8112HJ0C MIPI Receiver,DPHY RX V1.2; UMC 28nm HPC Logic and Mixed-Mode Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > MIPI
> MIPI DPHY > MIPI DPHY Transmitter 
Cell Name Descriptions Type Process Gradation Literature
FXDPHYTX1111HJ0C MIPI Transmitter 80Mbps~1.5Gbps ; UMC 28nm HPC Logic Process Analog_IP 28nm Contact Sales
 
FXDPHYTX1112HJ0C MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC Logic Process Analog_IP 28nm Contact Sales
 
FXDPHYTX4111HJ0C MIPI Transmitter 80Mbps~1.5Gbps ; UMC 28nm HPC Logic Process Analog_IP 28nm Contact Sales
 
FXDPHYTX4112HJ0C MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC Logic and Mixed-Mode Process Analog_IP 28nm Bronze
 
FXDPHYTX4112HJ0P MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC+ process Analog_IP 28nm Contact Sales
 
FXDPHYTX4212NSHJ0C MIPI Transmitter 80Mbps~2.5Gbps cost down ; UMC 28nm HPC process Analog_IP 28nm Contact Sales
 
FXDPHYTX8112HJ0C MIPI Transmitter 80Mbps~2.5Gbps ; UMC 28nm HPC Logic Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > MIPI
> On Die Termination for MIPI 
Cell Name Descriptions Type Process Gradation Literature
FXODT010NSHJ0C MIPI On-Die Termination ; UMC 28nm HPC process Analog_IP 28nm Contact Sales
 
 
Interface Solution > Serdes
> 1.25G to 8G Serdes > Chassis Management Module for 1.25G to 8G Serdes 
Cell Name Descriptions Type Process Gradation Literature
FXCMM0010HJ0C CMM lane operating from 1.25G~8G ,UMC 28nm HPC Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > Serdes
> 1.25G to 8G Serdes > TX+RX Lane Operating for 1.25G to 8G Serdes 
Cell Name Descriptions Type Process Gradation Literature
FXTXRX0010HJ0C Analog part of TX+RX lane operating at 1.25G~8Gbps , UMC 28nm HPC Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > Serdes
> 4-Lane 10G Serdes 
Cell Name Descriptions Type Process Gradation Literature
FXSERDES0410HJ0C 28nm HPC x4 lane 10 Gbps SERDES Analog_IP 28nm Contact Sales
 
 
Interface Solution > Serdes
> 4-Lane 12.5G Serdes 
Cell Name Descriptions Type Process Gradation Literature
FXSERDES0412HJ0P UMC 28nm HPC+, 4-Lane 1.25~12.5 Gbps SERDES Analog_IP 28nm Contact Sales
 
FXSERDES0416HJ0C UMC 28nm HPC/Low-K process , 1.25G-12.5Gbps 4-Lane SERDES Analog_IP 28nm Contact Sales
 
Interface Solution > Serdes
> 4-Lane 28G Serdes 
Cell Name Descriptions Type Process Gradation Literature
FXSERDES4280HJ0C 28Gb/s 4 lane high-speed SerDes; UMC 28nm HPC Logic Std/HS process Analog_IP 28nm Contact Sales
 
 
Interface Solution > USB/OTG
> USB PHY > USB 2.0 OTG PHY 
Cell Name Descriptions Type Process Gradation Literature
FZOTG2661HJ0C USB 2.0 On-The-Go PHY, analog part ; UMC 28nm HPC RVT Logic Process Analog_IP 28nm Contact Sales
 
FZOTG266HJ0C USB 2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process Analog_IP 28nm Silver Minus
FZOTG266HJ0P USB 2.0 On-The-Go PHY; UMC 28nm HPC+ RVT Logic Process Analog_IP 28nm Contact Sales
 
FZOTG268HJ0C USB2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process cost down from FZOTG266HJ0C_A Analog_IP 28nm Contact Sales
 
FZOTG268HJ0L USB 2.0 On-The-Go PHY; UMC 28nm HLP Process Analog_IP 28nm Contact Sales
 
Interface Solution > USB/OTG
> USB PHY > USB 3.0 OTG PHY 
Cell Name Descriptions Type Process Gradation Literature
FZOTG300HJ0C USB 3.0 PHY ; UMC 28nm HPC RVT+LVT Logic Process Analog_IP 28nm Bronze
FZOTG300HJ0P USB 3.0 PHY; UMC 28nm HPC_Plus +RVT+LVT Logic Process Analog_IP 28nm Contact Sales
 
 
Interface Solution > USB/OTG
> USB PHY > USB 3.1 PHY 
Cell Name Descriptions Type Process Gradation Literature
FZOTG306HJ0C Cost Down USB 3.1 Gen.1 PHY ; UMC 28nm HPC Logic Process Analog_IP 28nm Contact Sales
 
FZOTG306NSHJ0P USB 3.1 Gen1 PHY Costdown version ; UMC 28nm HPC+, SVT&LVT Logic Process A+D Part Naming with IO at North-South (NS) Analog_IP 28nm Contact Sales
 
FZOTG310HJ0C 28nm HPC USB3.1 gen2 PHY(10Gbps) Analog_IP 28nm Contact Sales
 
FZOTG310HJ0P 28nm HPC+ USB3.1 gen2 PHY(10Gbps) Analog_IP 28nm Contact Sales
 
 
Interface Solution > V-by-One
> VBO Receiver 
Cell Name Descriptions Type Process Gradation Literature
FXVBORX008HJ0C 600M to 4Gbps 4-lane V-By-One receiver, VCC=0.9V; UMC 28nm HPC LowK Logic Process. Analog_IP 28nm Contact Sales
FXVBORX008HJ0P Analog part of 600Mbps to 4Gbps 4-lane V-By-One receiver with embedded CDR circuit, VCC=0.9V; UMC 28nm HPC+ LowK Logic Process. Analog_IP 28nm Contact Sales
 
FXVBORX008NSHJ0C 28HPC VBO RX, 600Mbps~4Gbps, 4 lanes, bump version Analog_IP 28nm Contact Sales
 
 
Interface Solution > V-by-One
> VBO Transmitter 
Cell Name Descriptions Type Process Gradation Literature
FXVBOTX008HJ0P Analog part of 600Mbps to 4Gbps 8-lane V-By-One transmitter with embedded PLL circuit, VCC=0.9V; UMC 28nm HPC+ LowK Logic Process. Analog_IP 28nm Contact Sales