Logic Libraries Updated On:2018-04-25

Gradation Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below, Platinum P Five (5) productions verified Gold G Mass production proven Silver S Silicon proven, Formal release Silver Minus S- Manufacturing onging Bronze B Pre-Silicon release

 

Logic Libraries > PowerSlash Core Cell Library > 7-Track > 7T HVT PSK Library  Cell Name Descriptions Type Process Gradation Literature FSJ0C_DHS_POWERSLASH _CORE UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track PowerSlash Kit cell library C35 Library_Group 28nm Silver FSJ0C_EHS_POWERSLASH _CORE UMC 28nm HPC/HVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35) Library_Group 28nm Silver FSJ0L_EHS_POWERSLASH _CORE UMC 28nm HLP/HVT Logic and Mixed-Mode Process 7-track PowerSlash Cell Library Library_Group 28nm Silver FSJ0L_EHU_POWERSLASH _CORE UMC 28nm HLP/HVT Logic and Mixed-Mode Process 7-track Generic Core Cell Library with LPLUS (C-38) Library_Group 28nm Contact Sales FSJ0P_EHS_POWERSLASH _CORE UMC 28nm HPC+/HVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35) Library_Group 28nm Contact Sales   Logic Libraries > PowerSlash Core Cell Library > 7-Track > 7T LVT PSK Library  Cell Name Descriptions Type Process Gradation Literature FSJ0C_DLS_POWERSLASH _CORE UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-Track POWERSLASH cell library (C35) Library_Group 28nm Silver FSJ0C_ELS_POWERSLASH _CORE UMC 28nm HPC/LVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35) Library_Group 28nm Silver FSJ0L_ELD_POWERSLASH _CORE UMC 28nm HLP/LVT Logic and Mixed-Mode Process 7-track Powerslash Cell Library with LMINUS (C-30) Library_Group 28nm Contact Sales FSJ0L_ELS_POWERSLASH _CORE UMC 28nm HLP/LVT Logic and Mixed-Mode Process 7-track PowerSlash Cell Library Library_Group 28nm Silver FSJ0L_ELU_POWERSLASH _CORE UMC 28nm HLP/LVT Logic and Mixed-Mode Process 7-track Powerslash Generic Core Cell Library wtih LPLUS (C-38) Library_Group 28nm Contact Sales FSJ0P_ELS_POWERSLASH _CORE UMC 28nm HPC+/LVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35) Library_Group 28nm Contact Sales   Logic Libraries > PowerSlash Core Cell Library > 7-Track > 7T RVT PSK Library  Cell Name Descriptions Type Process Gradation Literature FSJ0C_DRS_POWERSLASH _CORE UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library (C35) Library_Group 28nm Silver FSJ0C_ERS_POWERSLASH _CORE UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35) Library_Group 28nm Silver FSJ0L_ERD_POWERSLASH _CORE UMC 28nm HLP/RVT Logic and Mixed-Mode Process 7-track Powerslash cell library with LMINUS (C-30 RVT) Library_Group 28nm Contact Sales FSJ0L_ERS_POWERSLASH _CORE UMC 28nm HLP/RVT Logic and Mixed-Mode Process 7-track Power Slash Cell Library Library_Group 28nm Silver FSJ0L_ERU_POWERSLASH _CORE UMC 28nm HLP/RVT Logic and Mixed-Mode Process 7-track Powerslash Cell Library with LPLUS (C-38) Library_Group 28nm Contact Sales   Logic Libraries > PowerSlash Core Cell Library > 7-Track > 7T SVT PSK Library  Cell Name Descriptions Type Process Gradation Literature FSJ0P_ERS_POWERSLASH _CORE UMC 28nm HPC+/SVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35) Library_Group 28nm Contact Sales