Dual-Port SRAM

Updated On:2018-04-21
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Memory Compiler > Dual-Port SRAM
> 6TSRAM > High Density DPSRAM, 6TSRAM, Peri LVT, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_L_SJLVT UMC 28nm HPC process PG-Dual Port SRAM with LVT Memory_IP 28nm Bronze
FSJ0C_L_SJLVTR1 UMC 28nm HPC process PG Dual Port SRAM with LVT Memory_IP 28nm Bronze
 
 
Memory Compiler > Dual-Port SRAM
> 6TSRAM > High Density DPSRAM, 6TSRAM, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_L_SJ UMC 28nm HPC process Dual Port SRAM with Power gating Memory_IP 28nm Bronze
FSJ0C_L_SJR1 UMC 28nm HPC Process dual port SRAM with power gating Memory_IP 28nm Bronze
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_A_SJ UMC 28nm HPC process Dual Port SRAM compiler Memory_IP 28nm Bronze
FSJ0C_A_SJR1 UMC 28nm HPC process Dual Port SRAM with row reapir Memory_IP 28nm Bronze
FSJ0C_L_SJHVT UMC 28nm HPC process standard synchronous high density dual port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0L_A_SJ UMC 28nm HLP/Low-k Dual-Port SRAM compiler Memory_IP 28nm Contact Sales
 
FSJ0L_A_SJR1 UMC 28nm HLP Logic Process ; Dual Port SRAM compiler with R1 Memory_IP 28nm Contact Sales
 
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_A_SJHVT UMC 28nm HPC process Dual Port SRAM compiler Memory_IP 28nm Bronze
FSJ0C_A_SJHVTR1 UMC 28nm HPC process Dual Port SRAM compiler Memory_IP 28nm Bronze
FSJ0C_L_SJHVTR1 UMC 28HPC process standard synchronous high density dual port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0P_A_SJHVT UMC 28nm HPC+ process dual port SRAM memory compiler with HVT+RVT peripheral Memory_IP 28nm Contact Sales
 
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_A_SJLVT UMC 28nm HPC process Dual Port SRAM with LVT Memory_IP 28nm Bronze
FSJ0C_A_SJLVTR1 UMC 28nm HPC process Dual Port SRAM with row repair & LVT Memory_IP 28nm Bronze
FSJ0L_A_SJLVT UMC 28nm HLP Logic Process ; Dual Port SRAM compiler with LVT Memory_IP 28nm Contact Sales