Memory Compiler

Updated On:2018-04-23
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_B_SHLVT UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler. Memory_IP 28nm Silver Minus
FSJ0C_B_SHLVTR1 UMC 28nm Logic process standard synchronous LVT periphery high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0C_D_SHLVT UMC 28nm HPC process synchronous LVT periphery high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0C_D_SHLVTR1 UMC 28nm HPC Process Synchronous LVT/RVT Periphery High Density Single Port SRAM Memory Compiler with Row Redundancy Memory_IP 28nm Contact Sales
 
FSJ0L_B_SHLVT UMC 28nm HLP Logic process LVT standard synchronous high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0L_B_SHLVTC1 UMC 28nm HLP process standard LVT synchronous high density single port SRAM memory compiler. Memory_IP 28nm Contact Sales
 
FSJ0L_B_SHLVTR1 UMC 28nm HLP Logic process LVT standard synchronous high density single port SRAM memory compiler. Memory_IP 28nm Bronze
FSJ0L_B_SHLVTR1C1 UMC 28nm HLP process LVT standard synchronous high density single port SRAM memory compiler. Memory_IP 28nm Contact Sales