Interface Solution

Updated On:2018-06-23
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Interface Solution > DDR
> DDR Controller > DDR3 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3PHYD100EWHJ0C DDR3 RTL Digitalize PHY DATA block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS Analog_IP 28nm Contact Sales
 
FXDDR3PHYD100NSHJ0C DDR3 RTL Digitalize PHY DATA block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS Analog_IP 28nm Contact Sales