Logic Libraries

Updated On:2018-04-23
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Logic Libraries > PowerSlash Core Cell Library
> 7-Track > 7T RVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSJ0C_DRS_POWERSLASH
_CORE
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library (C35) Library_Group 28nm Silver
FSJ0C_ERS_POWERSLASH
_CORE
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 7-track POWERSLASH cell library enhanced for routing (C35) Library_Group 28nm Silver
FSJ0L_ERD_POWERSLASH
_CORE
UMC 28nm HLP/RVT Logic and Mixed-Mode Process 7-track Powerslash cell library with LMINUS (C-30 RVT) Library_Group 28nm Contact Sales
 
FSJ0L_ERS_POWERSLASH
_CORE
UMC 28nm HLP/RVT Logic and Mixed-Mode Process 7-track Power Slash Cell Library Library_Group 28nm Silver
FSJ0L_ERU_POWERSLASH
_CORE
UMC 28nm HLP/RVT Logic and Mixed-Mode Process 7-track Powerslash Cell Library with LPLUS (C-38) Library_Group 28nm Contact Sales