Analog

Updated On:2018-01-19
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Analog > Clock
> All Digital Delay Line > over 1G, All Digital Delay Line 
Cell Name Descriptions Type Process Gradation Literature
FXDCDL341HJ0C Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process Analog_IP 28nm Contact Sales
FXDCDL341HJ0G Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPM Process Analog_IP 28nm Bronze
FXDCDL342HJ0C Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 50% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process Analog_IP 28nm Contact Sales
FXDCDL342HJ0G Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 50% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPM Process Analog_IP 28nm Bronze
FXDCDL343HJ0C Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 25% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process Analog_IP 28nm Contact Sales
FXDCDL343HJ0G Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 25% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPM Process Analog_IP 28nm Bronze