Interface Solution

Updated On:2018-04-25
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Interface Solution > LVDS
> FPD LVDS Receiver 
Cell Name Descriptions Type Process Gradation Literature
FXLVRX020HJ0C LVDS RX Receives serial LVDS signal and de-serialize them into parallel format ; UMC 28nm HPC Logic Process Analog_IP 28nm Contact Sales
FXLVRX020HJ0P UMC 28nm HPC+ Logic Process, LVDS RX Receives serial LVDS signal and de-serialize them into parallel format Analog_IP 28nm Contact Sales