Clock

Updated On:2018-01-24
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Analog > Clock
> All Digital Delay Line > 20M ~ 500M, All Digital Delay Line 
Cell Name Descriptions Type Process Gradation Literature
FXDCDL201HH0L Input 50M-210MHz, output 50M-210MHz. An all digital slave delay line of FXADDLL200HH0L to generate Programmable delay per 1/32 UI delay line UMC 40nm LP Logic Process Analog_IP 40nm Bronze
 
Analog > Clock
> All Digital Delay Line > 500M ~ 1G, All Digital Delay Line 
Cell Name Descriptions Type Process Gradation Literature
FXDCDL331HH0L Input 360M-720MHz, output 360M-720MHz, all digital slave delay line of FXADDLL330HH0L to generate programmable delay in period of FREF,UMC 40nm LP Process Analog_IP 40nm Bronze
FXDCDL351HH0L Input 360M-720MHz, output 360M-720MHz, all digital slave delay line of FXADDLL330HH0L to generate programmable delay in period of FREF, UMC 40nm LP Process Analog_IP 40nm Bronze
 
Analog > Clock
> All Digital Delay Line > over 1G, All Digital Delay Line 
Cell Name Descriptions Type Process Gradation Literature
FXDCDL341HH0L Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Process Analog_IP 40nm Bronze
FXDCDL342HH0L Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Process . Analog_IP 40nm Bronze
FXDCDL343HH0L Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 40nm Logic Process Analog_IP 40nm Bronze
FXDCDL344HH0L Input 400M-1600MHz, output 400M-1600MHz, all digital slave delay line of FXADDLL340HH0L to generate 25% delay in period of FREF, UMC 40nm LP/RVT Logic Process. Analog_IP 40nm Bronze
 
Analog > Clock
> DLL > 20M ~ 500M, DLL 
Cell Name Descriptions Type Process Gradation Literature
FXDLL340HH0L Input 80MHz-280MHz, DQS delay 6.25%-50% of FREF period, UMC 40nm LP/RVT Low-K logic process. Analog_IP 40nm Silver Minus
FXDLL344HH0L Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process. Analog_IP 40nm Bronze
 
Analog > Clock
> Digitized DLL > 20M ~ 500M, Digitalized DLL 
Cell Name Descriptions Type Process Gradation Literature
FXADDLL200HH0L An ADDLL operate at 50MHz~210MHz. Supports slave delay line to generate per 1/32 UI programmable delay UMC 40nm LP/RVT Logic Process. Analog_IP 40nm Bronze
 
Analog > Clock
> Digitized DLL > 500M ~ 1G, Digitalized DLL 
Cell Name Descriptions Type Process Gradation Literature
FXADDLL310HH0L Input 333M-800MHz, output 333M-800MHz, all digital DLL with one-channel DQS delay range ; UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Silver Minus
FXADDLL330HH0L An ADDLL operate at 300MHz~600MHz. Output 0-180 degree Phase adjustment range. Delay adjustment resolution <= 1% of reference clock UMC 40nm LP/RVT Logic Process. Analog_IP 40nm Silver
FXADDLL350HH0L Input 360M-720M Hz, output 360M-720M Hz, DLL;Output 0-180 degree Phase adjustment range. UMC 40nm LP process. Analog_IP 40nm Bronze
 
Analog > Clock
> Digitized DLL > over 1G, Digitalized DLL 
Cell Name Descriptions Type Process Gradation Literature
FXADDLL340HH0L Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 40nm Logic Process. Analog_IP 40nm Bronze
 
Analog > Clock
> LC-PLL > 20M ~ 500M, LC-PLL 
Cell Name Descriptions Type Process Gradation Literature
FXLCPLL101HH0L Jitter clean integer-N LC-PLL for serdes, output frequency is 156.25M, input frequency is 25M for Low-Jitter Mode, 156.25M for Jitter-Clean Mode. UMC 40nm LP LowK Logic Process. Analog_IP 40nm Contact Sales
 
 
Analog > Clock
> Oscillator 
Cell Name Descriptions Type Process Gradation Literature
FXLCOSC012HH0L XTAL LESS for USB3.0 ; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Bronze
FXOSC002HH0L Internal-RC, frequency 1.8432MHz or 2.4576MHz, Input 1.045V-1.155V, VBG=0.8V Oscillator. UMC 40nm LP/RVT Logic Process. Analog_IP 40nm Silver Minus
FXOSC032HH0L Internal-R,output frequency 32 KHz, Input 0.99V-1.21V Oscillator. UMC 40nm LP/RVT Logic Process. Analog_IP 40nm Silver
FXOSC048HH0L InternalRC OSC, optional outout frequency 48MHz/24MHz/16MHz/12MHz, input VBG=0.8V; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Silver Minus
FXOSC054HH0L Internal RC OSC, optional outout frequency 54MHz/27MHz/18MHz/13.5MHz, input VBG=0.8V; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Bronze
 
Analog > Clock
> Others 
Cell Name Descriptions Type Process Gradation Literature
FXS2D101HH0L IP name: FXS2D101HH0L Area: 300um*300um Analog_IP 40nm Silver
 
Analog > Clock
> PLL > 20M ~ 500M, Generic PLL 
Cell Name Descriptions Type Process Gradation Literature
FXPLL010HH0L Input 10-50M Hz, output 10-200M Hz, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Silver
FXPLL010HH0L_FTC Input 10-50M Hz, output 10-200M Hz, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process(Note:same schematic with FXPLL010HH0L, but Poly Density Errors are waived in layout for 40% area reduced.) Analog_IP 40nm Bronze
FXPLL125HH0L Input 12M Hz, output clock1 540M Hz and output clock2 120M Hz, PLL; UMC 40nm LP/RVT Low-K Logic Process Analog_IP 40nm Silver Minus
FXPLL134HH0L miniPLL (TM) Phase-Locked Loop (PLL) with an operating frequency range of between 250 MHz and 500 MHz ; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Bronze
FXPLL360HH0L_LTE2 Input 25M~440MHz, output 267M-533M, 200M-400M and 160M-320M, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
FXPLL362HH0L Input 200MHz - 400MHz, output clock_1X 200MHz - 400MHz, output clock_2X 400MHz - 800MHz, output clock_4X 800MHz-1600MHz,frequency synthesizable PLL;UMC 40nm LP/RVT LowK Logic process Analog_IP 40nm Silver Minus
 
Analog > Clock
> PLL > 500M ~ 1G, Generic PLL 
Cell Name Descriptions Type Process Gradation Literature
FXPLL360HH0L Input 25M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Silver
FXPLL510HH0L_DPHY Input 6M-27M Hz, output 10M-850M Hz, frequency synthesizable PLL; UMC 40nm Logic LP RVT and LVT process Analog_IP 40nm Silver
FXPLLLV362HH0L This IP for DDR4, Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400MHz - 1600MHz, output,frequency synthesizable PLL; UMC 40nm LP Logic Process Analog_IP 40nm Contact Sales
 
Analog > Clock
> PLL > over 1G, Generic PLL 
Cell Name Descriptions Type Process Gradation Literature
FXPLL110HH0L Input 10M-200M Hz, output 62.5M-1G Hz, frequency synthesizable PLL; UMC 40 nm LP/RVT Low-K Logic Process Analog_IP 40nm Silver
FXPLL120HH0L Input 20M-200M Hz, output 500M-1G Hz, frequency synthesizable PLL; UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Silver
 
Analog > Clock
> SSCG > 500M ~ 1G, SSCG 
Cell Name Descriptions Type Process Gradation Literature
FXSSCG360HH0L Input clock:25~66MHz, output clock range:400 ~ 800 MHz wide-range SSCG; UMC 40nm LP/RVT process. Analog_IP 40nm Silver
 
Analog > Clock
> SSCG > over 1G, SSCG 
Cell Name Descriptions Type Process Gradation Literature
FXSSCG602HH0L Input clock range:5 ~ 1280 MHz, output clock range:15.625 ~ 2000 MHz wide-range SSCG; UMC UMC 40nm LP/LVT LowK Logic Process Analog_IP 40nm Silver
FXSSCG603HH0L Input clock:8MHz, output clock range:720 ~ 1680 MHz wide-range SSCG; UMC 40nm LP process. Analog_IP 40nm Silver