Memory Compiler

Updated On:2018-04-22
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density & Low Power 1PRF, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_H_SY UMC 40nm Low Power Process One Port Register File with 213 cell Memory_IP 40nm Silver Minus
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density & Low Power 1PRF, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_H_SYHVT UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with HVT peripheral. Memory_IP 40nm Silver Minus
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density & Low Power 1PRF, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_H_SYLVT UMC 40nm low power process standard synchronous one port register file SRAM memory compiler with LVT peripheral. Memory_IP 40nm Silver Minus
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_B_SY UMC 40nm LP/HVT Logic Process with 6TSRAM (0.242 mm2) 1-port Register File Memory Compiler Memory_IP 40nm Silver
FSH0L_G_SQLVT UMC 40nm LP Logic Process Ultra High Speed One-Port Register File Memory_IP 40nm Silver
FSH0L_L_SY 40LP 1PRF with Sleep/retention/Nap mode feature Memory_IP 40nm Silver
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM, Peri HVT, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSH0U_A_SYHVT UMC 40nm uLP Logic Process 1-Port Register File with Peri-HVT Memory_IP 40nm Contact Sales
 
 
Memory Compiler > 1-Port Register File
> 6TSRAM > High Density 1PRF, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_B_SYLVT UMC 40nm LP Logic Process single port register file memory compiler with LVT periphery Memory_IP 40nm Silver
FSH0L_L_SYLVT 40LP 1PRF with Sleep/Retention/Nap mode & peri LVT feature Memory_IP 40nm Silver
 
Memory Compiler > 1-Port Register File
> 6TSRAM > Ultra High Speed 1PRF, 6TSRAM  
Cell Name Descriptions Type Process Gradation Literature
FSH0L_D_SY UMC 40nm Low Power Process One Port Register File wit 213 cell Memory_IP 40nm Silver Minus
 
Memory Compiler > 1-Port Register File
> 6TSRAM > Ultra High Speed 1PRF, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_D_SYHVT UMC 40nm LP Logic Process one-port register file for area optimize with HVT peripheral Memory_IP 40nm Silver Minus
FSH0V_D_SYHVT UMC 40nm embedded high voltage (eHV) low power Process standard synchronous high density single port register file SRAM memory compiler. Memory_IP 40nm Bronze
 
Memory Compiler > 1-Port Register File
> 6TSRAM > Ultra High Speed 1PRF, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_D_SYLVT UMC 40nm LP Logic Process one-port register file for area optimize with LVT peripheral Memory_IP 40nm Silver Minus
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density & Low Power 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_L_SH ULL Single Port SRAM ,UMC 40nm LP process. Memory_IP 40nm Silver
FSH0L_L_SHRED ULL Single Port SRAM with row redundancy , UMC 40nm LP Process. Memory_IP 40nm Silver Minus
FSH0U_B_SH UMC 40nm Low K Ultra Low Power Logic Process High-Density Single Port SRAM Compiler Memory_IP 40nm Contact Sales
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density & Low Power 1PSRAM, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_L_SHHVT ULL Single Port SRAM with peri HVT, UMC 40nm LP process. Memory_IP 40nm Bronze
FSH0L_L_SHHVTRED ULL Sigle Port SRAM with HVT Row redundancy, UMC 40nm LP process. Memory_IP 40nm Silver Minus
FSH0L_L_SHLVT UMC 40nm LP/LVT SP-SRAM compiler with peri-LVT and Power gating Memory_IP 40nm Bronze
FSH0L_L_SHLVTRED UMC 40nm LP/LVT SP-SRAM compiler with power gating & row redundancy Memory_IP 40nm Bronze
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density & Ultra Low Power 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSH0U_B_SHHVT UMC 40nm Low K Ultra Low Power Logic Process High-Density Single Port SRAM Compiler Memory_IP 40nm Contact Sales
FSH0U_B_SHRED UMC 40nm Low K Ultra Low Power Logic Process High-Density Single Port SRAM Compiler Memory_IP 40nm Contact Sales
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_B_SH UMC 40nm LP/HVT Logic Process with 6TSRAM (0.242 mm2) One Port SRAM Memory Compiler Memory_IP 40nm Silver
FSH0L_B_SHRED UMC 40nm LP Logic Process Single Port SRAM memory compiler with row redundancy Memory_IP 40nm Silver
FSH0L_D_SH UMC 40nm Low Power Process SP-SRAM with 213 bit cell Memory_IP 40nm Silver Minus
FSH0L_D_SHRED UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell Memory_IP 40nm Bronze
FSH0L_H_SH UMC 40nm Low Power Process Single-Port SRAM 213cell with power gating Memory_IP 40nm Silver Minus
FSH0L_H_SHRED UMC 40nm Low Power Process PG SP-SRAM with Row redundancy for 213 bit cell Memory_IP 40nm Bronze
FSH0L_K_SH UMC 40nm Low Power Process Single-Port SRAM for dual power rail Memory_IP 40nm Bronze
FSH0L_L_SYHVT UMC 40nm LP with power gating & peri-HVT 1PRF Memory_IP 40nm Contact Sales
 
FSH0U_L_SYHVT UMC 40nm uLP process ULL One Port Register File memory compiler Memory_IP 40nm Bronze
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_D_SHHVT UMC 40nm LP Logic Process Single Port SRAM memory compiler using 213 bit -cell with peri-HVT Memory_IP 40nm Silver Minus
FSH0L_H_SHHVT UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-HVT Memory_IP 40nm Silver Minus
FSH0U_B_SHHVTRED UMC 40nm Low K Ultra Low Power Logic Process High-Density Single Port SRAM Compiler Memory_IP 40nm Contact Sales
FSH0U_L_SHHVT UMC 40nm uLP process ULL Single-Port SRAM Memory_IP 40nm Contact Sales
 
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > High Density 1PSRAM, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_A_SEREDLVT UMC 40nm LP Logic Process Ultra High-Speed Single Port SRAM Memory compiler with Redundancy Memory_IP 40nm Silver Minus
FSH0L_B_SHLVT UMC 40nm LP Logic Process Single Port SRAM Compiler with LVT Periphery Memory_IP 40nm Silver
FSH0L_B_SHREDLVT UMC 40nm LP Logic Process Single Port SRAM Compiler LVT with row redundancy Memory_IP 40nm Silver
FSH0L_D_SHLVT UMC 40nm LP Logic Process Single Port SRAM Memory Compiler using 213 bit-cell with Peri-LVT Memory_IP 40nm Silver Minus
FSH0L_D_SHLVTRED UMC 40nm LP process synchronous high density (0.213LPHVT cell) single port SRAM compiler with row redundancy. Memory_IP 40nm Bronze
FSH0L_G_SELVT UMC 40um LP Logic Process High Speed Singl Port SRAM Compiler with 303RVT cell and Peri LVT Memory_IP 40nm Silver
FSH0L_H_SHLVT UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-LVT Memory_IP 40nm Silver Minus
FSH0L_H_SHLVTRED 40LP PG SP-SRAM LVT Peripheral with Row redundancy for 213 cell Memory_IP 40nm Bronze
 
Memory Compiler > 1-Port SRAM
> 6TSRAM > Ultra High Speed 1PSRAM, 6TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_A_SELVT UMC 40LP 303HVT cell /Peri-LVT Memory_IP 40nm Silver Minus
 
Memory Compiler > 2-Port Register File
> 6TSRAM > High Density and Ultra Low Power 2PRF, 6TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSH0U_B_SV UMC 40nm logic Ultra Low Power Process Two Port Register File memory compiler(with 6T SRAM cell) Memory_IP 40nm Contact Sales
 
Memory Compiler > 2-Port Register File
> 6TSRAM > High Density and Ultra Low Power 2PRF, 6TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0U_B_SVHVT UMC 40nm logic ultra low power process two port register file SRAM memory compiler(with 6T SRAM cell) Memory_IP 40nm Contact Sales
 
Memory Compiler > 2-Port Register File
> 8TSRAM > High Density 2PRF, 8TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_A_SZ UMC 40nm LP/RVT LowK Logic 2-Port Register File Memory Compiler Memory_IP 40nm Silver
FSH0L_B_SZ UMC 40nm LP/Low-K process ; Two Port Register File memory compiler Memory_IP 40nm Silver
FSH0L_L_SZ 40LP 2PRF with Sleep/Retention/Nap mode feature Memory_IP 40nm Silver Minus
 
Memory Compiler > 2-Port Register File
> 8TSRAM > High Density 2PRF, 8TSRAM, Dual Power Rail 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_T_SZ UMC 40nm Low Power Process , Two Port Register File with dual power rail Memory_IP 40nm Contact Sales
 
Memory Compiler > 2-Port Register File
> 8TSRAM > High Density 2PRF, 8TSRAM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_L_SZHVT UMC 40nm Logic process standard Synchronous High Density Two Port Register File SRAM memory compiler. Memory_IP 40nm Contact Sales
 
Memory Compiler > 2-Port Register File
> 8TSRAM > High Density 2PRF, 8TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_A_SZLVT UMC 40nm LP Logic Process Two-Port Register File with LVT Peripheral Memory Compiler Memory_IP 40nm Contact Sales
 
FSH0L_B_SZLVT UMC 40nm LP/LVT Process; Two Port Register File with LVT Memory_IP 40nm Silver
FSH0L_L_SZLVT 40LP 2PRF with Sleep/Retention/Nap mode & peri LVT feature Memory_IP 40nm Silver Minus
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_A_SJ UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler. Memory_IP 40nm Silver
FSH0L_A_SJRED UMC 40nm Logic Process standard synchronous high density dual port SRAM memory compiler with redundancy Memory_IP 40nm Silver
FSH0L_C_SJ 40LP High density dual port SRAM compiler with Vss booster feature Memory_IP 40nm Silver Minus
FSH0L_C_SJRED UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy Memory_IP 40nm Silver Minus
FSH0L_T_SJ UMC 40nm Low Power Process Dual-Port SRAM compiler with dual power rail Memory_IP 40nm Bronze
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM, Peri HVT, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_L_SJHVTRED UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler Memory_IP 40nm Contact Sales
 
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_A_SJLVT UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with LVT Memory_IP 40nm Silver
FSH0L_A_SJREDLVT UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with ROW redundancy with LVt peripheral Memory_IP 40nm Silver
FSH0L_C_SJLVT UMC 40nm LP Logic Process Dual-Port SRAM Memory Compiler with LVT peripheral Memory_IP 40nm Silver Minus
FSH0L_C_SJLVTRED UMC 40nm LP Logic Process Dual-Port SRAM memory compiler with redundancy and LVT peripheral Memory_IP 40nm Silver Minus
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM, Peri LVT, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_L_SJLVT UMC 40nm LP LowK Logic Process ULL Dual-Port SRAM Memory Compiler with Peri-LVT Memory_IP 40nm Silver Minus
FSH0L_L_SJLVTRED UMC 40NM Low-K Low Power synchronous Feature Dual Port SRAM memory compiler Memory_IP 40nm Bronze
 
Memory Compiler > Dual-Port SRAM
> 8TSRAM > High Density DPSRAM, 8TSRAM, Power Gating 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_L_SJ UMC 40nm LP Dual Port SRAM compiler with Sleep/Retention mode Memory_IP 40nm Silver Minus
FSH0L_L_SJRED UMC 40nm Low-K Low Power synchronous Feature Dual Port SRAM memory compiler Memory_IP 40nm Silver Minus
 
Memory Compiler > ROM
> VIA1 ROM > VIA1 ROM 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_A_SP UMC 40 LP/RVT LowK Logic Process Via1 ROM Memory Compiler Memory_IP 40nm Silver
FSH0L_B_SP UMC 40nm LP Logic Process Via ROM compiler with WL booster Memory_IP 40nm Silver
 
Memory Compiler > ROM
> VIA1 ROM > VIA1 ROM, Peri HVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0U_A_SPHVT UMC 40nm ultra low power via1 ROM complier Memory_IP 40nm Bronze
FSH0U_L_SPHVT UMC 40nm uLP process ULL Via1 ROM compiler Memory_IP 40nm Bronze
 
Memory Compiler > ROM
> VIA1 ROM > VIA1 ROM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_B_SPLVT UMC 40nm LP Logic Process Via ROM compiler with peri LVT and WL booster Memory_IP 40nm Silver
 
Memory Compiler > ROM
> VIA1 ROM > VIA1 ROM, Sleep Mode 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_L_SP UMC 40LP Via1 ROM compiler with Sleep mode Memory_IP 40nm Silver
 
Memory Compiler > ROM
> VIA1 ROM > VIA1 ROM, Sleep Mode, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_L_SPLVT UMC 40LP via1 ROM compiler with Sleep mode & peri LVT Memory_IP 40nm Silver
 
Memory Compiler > TCAM SRAM
> High Density TCAM 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_A_SF UMC 40nm LP process standard synchronous high density TCAM memory compiler. Memory_IP 40nm Bronze
 
Memory Compiler > TCAM SRAM
> High Density TCAM, Peri LVT 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_A_SFLVT UMC 40nm LP Logic Process TCAM with LVT peripheral memory compiler Memory_IP 40nm Bronze