Interface Solution

Updated On:2018-06-21
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Interface Solution > DDR
> DDR IO > DDR2 - SSTL18 IO Library 
Cell Name Descriptions Type Process Gradation Literature
FOH0L_QRS25_T18_SSTL
18A_IO
40LP DDR3 IO PG lib IP (characterized voltage: 1.8V). Library_Group 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Combo > DDR3/3L - Combo Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3LTA102HH0L DDR3/DDR3L/LPDDR2 combo PHY ( not support DDR3 leveling function), command / address block,UMC 40nm LP/RVT LowK Logic Process. Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR3 PHY - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4AFC602HH0L Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR3/3L - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3A100HH0L DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device Analog_IP 40nm Silver
FXDDR3A502HH0L Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process Analog_IP 40nm Silver
FXDDR3A503HH0L DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
FXDDR3AFC502HH0L DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR4 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4AFC101HH0L DDR34 COMBO PHY ADDR Block for Solder bump Flip chip version ;UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
FXDDR4AFD612HH0L Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version; UMC 40nm LP LVT/RVT LowK Logic Process Analog_IP 40nm Contact Sales
 
Interface Solution > DDR
> DDR PHY - Command/Address > LPDDR2 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXLPDDR2A102HH0L_SIP 40nm LPDDR2-PHY command/address block for SIP Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Command/Address > LPDDR3 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXLPDDR3AW101HH0L LPDDR3-PHY Command/address block for LightCo ; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Compensation > DDR3/3L - Compensation 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3COMP100HH0L DDR23 COMBO PHY compensation Block ; UMC 40LP/RVT LowK Logic Process with 2.5V device Analog_IP 40nm Silver
FXDDR3COMPFC502HH0L DDR3 Combo PHY Compensation Block for solder bump application; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
FXDDR3LTCOMP100HH0L compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process . Analog_IP 40nm Silver
FXDDR3LTCOMP100HH0L compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process . Analog_IP 40nm Silver
FXDDR3LTCOMP100HH0L compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process . Analog_IP 40nm Silver
FXDDR3LTCOMP100HH0L compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process . Analog_IP 40nm Silver
 
Interface Solution > DDR
> DDR PHY - Compensation > DDR4 - Compensation 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4COMP101HH0L UMC 40nm LP process DDR34/LPDDR23 COMPENSATION Block with 2.5V Device Analog_IP 40nm Contact Sales
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR3/3L - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3D100HH0L DDR23 COMBO PHY Data Block ; UMC 40nm LP/RVT LowK Logic Process with 2.5V device Analog_IP 40nm Silver
FXDDR3D502HH0L Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process Analog_IP 40nm Silver Minus
FXDDR3DFC502HH0L DDR3 Combo PHY Data Block for solder bump application; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
FXDDR3LTD102HH0L DDR3/DDR3L/LPDDR2 combo PHY ( not support DDR3 leveling function), data block;UMC 40nm LP/RVT LowK Logic Process . Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR4 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4D16FC101HH0L 40nm LP DDR3/4 LPDDR23 COMBO PHY DATA Block for Flip Chip usage Analog_IP 40nm Contact Sales
 
FXDDR4DFD612HH0L Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process Analog_IP 40nm Contact Sales
 
Interface Solution > DDR
> DDR PHY - Data Block > DDR4 PHY - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXDDR4D16FC602HH0L Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Data Block > LPDDR2 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXLPDDR2D102HH0L_SIP 40nm LPDDR2-PHY data block for SIP Analog_IP 40nm Contact Sales
 
 
Interface Solution > DDR
> DDR PHY - Data Block > LPDDR3 - Data Block 
Cell Name Descriptions Type Process Gradation Literature
FXLPDDR3D16W101HH0L 40nm LPDDR3-PHY Data block for LightCo ; UMC 40nm LP/LVT Logic Process Analog_IP 40nm Contact Sales
 
 
Interface Solution > Ethernet
> Ethernet PHY > 10/100 TX Ethernet PHY 
Cell Name Descriptions Type Process Gradation Literature
FXEDP110HH0L 10/100 Base-TX Energy Efficient Ethernet PHY; UMC 40nm LP/RVT Low-K Logic Process Analog_IP 40nm Silver Minus
 
Interface Solution > Ethernet
> Ethernet PHY > 10/100/1000 TX Ethernet PHY 
Cell Name Descriptions Type Process Gradation Literature
FXEDP410HH0L 10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 40nm LP/RVT Low-K Logic Process Analog_IP 40nm Contact Sales
 
 
Interface Solution > LVDS
> FPD LVDS BIAS Circuit 
Cell Name Descriptions Type Process Gradation Literature
FXLVBGR030HH0L 10 lane FXSLVTX030HH0L bias circuit ; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Silver
 
Interface Solution > LVDS
> FPD LVDS Receiver 
Cell Name Descriptions Type Process Gradation Literature
FXLVDSRX060HH0L LVDS RX,UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Silver
FXLVDSRX080HH0L LVDS RX IO PAD 500 Mbps ,UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Contact Sales
 
FXLVDSRX080HH0L_BUMP LVDS RX IO PAD 500 Mbps, UMC 40nm LP/RVT LowK Logic Process, Bump pad. Analog_IP 40nm Contact Sales
 
FXLVIORX800HH0L 1.8v LVDS RX IO 800Mbps, UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Contact Sales
FXLVRX020HH0L 3.3v LVDS RX,UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Contact Sales
 
FXLVRX030HH0L 3.3v LVDS RX, 3 data lane and 1 clock lane using UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Bronze
FXLVRX038HH0L 8 Lanes LVDS RX IO PAD, UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Contact Sales
 
FXLVRX050HH0L 3.3v LVDS RX IO 1.25Gbps, UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Contact Sales
 
FXLVRX080HH0L LVDS RX IO PAD 500 Mbps, UMC 40nm LP/RVT LowK Logic Process, for flip chip Analog_IP 40nm Contact Sales
 
FXLVRX5308HH0L 5-Data Channel DLL-based LVDS RX ; 40LP/RVT low-K process ; 3.3V IO / 1.1V Core ; Clock Range 16Mhz~120Mhz Analog_IP 40nm Contact Sales
FXLVRXBS050HH0L The bias block only for FXLVRX050HH0L, UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Contact Sales
 
FXLVRXBS080HH0L The bias block only for FXLVDSRX080HH0L, UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Contact Sales
 
 
Interface Solution > LVDS
> FPD LVDS Transmitter 
Cell Name Descriptions Type Process Gradation Literature
FXLVTX020HH0L 2.5V FPD-link LVDS Transmitter 16~178.6MHz; UMC 40nm LP Low-K process Analog_IP 40nm Bronze
FXLVTX030HH0L 2.5V LVDS Transmitter 700Mbps; UMC 40nm LP LowK Logic Process Analog_IP 40nm Bronze
FXLVTX030HH0L_BUMP 2.5V LVDS Transmitter 700Mbps; UMC 40nm LP LowK Logic Process. (Modify layout ) Analog_IP 40nm Contact Sales
 
FXLVTX040HH0L 3.3V LVDS Transmitter 700Mbps; UMC 40nm LP LowK Logic Process Analog_IP 40nm Bronze
FXLVTX050HH0L 2.5V LVDS Transmitter 1.25Gbps; UMC 40nm LP LowK Logic Process. Analog_IP 40nm Bronze
FXLVTX100HH0L 100MHz single-ended to differential clock buffer for UMC 40nm LP. Analog_IP 40nm Bronze
 
Interface Solution > LVDS
> IO LVDS Receiver 
Cell Name Descriptions Type Process Gradation Literature
FXLVIORX1110HH0L LVDS RX IO PAD 1000 Mbps, UMC 40nm LP/RVT LowK Logic Process. Analog_IP 40nm Contact Sales
 
Interface Solution > LVDS
> IO LVDS Transmitter 
Cell Name Descriptions Type Process Gradation Literature
FXLVIOTX1307HH0L LVDS Combo-IO TX 750Mbps; UMC 40LP LowK Process; 3.3V IO / 1.1V Core; Include BGA Analog_IP 40nm Contact Sales
 
Interface Solution > LVDS
> Sub-LVDS Transmitter 
Cell Name Descriptions Type Process Gradation Literature
FXSLVTX030HH0L 1.8V Sub-LVDS Transmitter 1200Mbps; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Silver
 
Interface Solution > MIPI
> MIPI DPHY > MIPI DPHY Receiver 
Cell Name Descriptions Type Process Gradation Literature
FXDPHYRX420HH0L MIPI Receiver 80Mbps-1.5Gbps; 40nm LP LowK Logic Process Analog_IP 40nm Silver
FXDPHYRX420HH0L_GPIO MIPI Receiver 80Mbps-1Gbps; 40nm LP LowK Logic Process Analog_IP 40nm Silver
FXMPRX010HH0L MIPI Receiver 80Mbps-1.5Gbps; 40nm LP LowK Logic Process Analog_IP 40nm Silver Minus
FXMPRX020HH0L MIPI Receiver 80Mbps-1Gbps; Combo PHY for MIPI & HiSPi & LVDS & SubLVDS,40nm LP LowK Logic Process Analog_IP 40nm Silver Minus
FXMPRX030HH0L MIPI Receiver 80Mbps-1Gbps; Combo PHY for MIPI & HiSPi & LVDS & SubLVDS,40nm LP LowK Logic Process, Two Lane. Analog_IP 40nm Silver Minus
 
Interface Solution > MIPI
> MIPI DPHY > MIPI DPHY Transmitter 
Cell Name Descriptions Type Process Gradation Literature
FXDPHYTX210HH0L MIPI Transmitter 80Mbps~1.5Gbps with 1-clock lane, 2-data lanes; UMC 40nm LP/RVT/LVT Low-K process Analog_IP 40nm Contact Sales
 
FXDPHYTX411HH0L MIPI Transmitter 80Mbps~1.5Gbps; UMC 40nm LP/RVT/LVT Low-K process Analog_IP 40nm Contact Sales
 
FXDPHYTX430HH0L MIPI Transmitter 80Mbps~1500Mbps combo with CMOS input; UMC 40nm LP Low-K process Analog_IP 40nm Silver
FXMPTX010HH0L MIPI Transmitter 80Mbps~1500Mbps; UMC 40nm LP/RVT Low-K process Analog_IP 40nm Silver Minus
 
Interface Solution > MIPI
> MPHY > MIPI MPHY PMA 
Cell Name Descriptions Type Process Gradation Literature
FXMPHY010HH0L MIPI MPHY 6Gbps/lane; UMC 40nm LP Low-K process. Analog_IP 40nm Contact Sales
 
 
Interface Solution > ONFI4.0
> ONFI PHY 
Cell Name Descriptions Type Process Gradation Literature
FXONFI4COMP100HH0L ONFI PHY Compensation Block for ONFI4.0 application; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
 
Interface Solution > USB/OTG
> USB PHY > USB 2.0 OTG PHY 
Cell Name Descriptions Type Process Gradation Literature
FZOTG266HH0L OTG USB2.0 UMC 40 nm LP/RVT process Analog_IP 40nm Silver
FZOTG266HH0L_LF USB2.0 OTG PHY UMC 40nm LP/RVT process, for Flip chip Bump type_LF Analog_IP 40nm Contact Sales
 
FZOTG268HH0L USB 2.0 On-The-Go PHY; UMC 40nm Logic LP/RVT Low-K Process Analog_IP 40nm Bronze
 
Interface Solution > USB/OTG
> USB PHY > USB 2.0 OTG Two-Port PHY 
Cell Name Descriptions Type Process Gradation Literature
FZOTGTP201HH0L Two Port OTG USB2.0 PHY;BOAC version; Wire bonding;UMC 40 nm LP/RVT process. Analog_IP 40nm Silver Minus
 
Interface Solution > USB/OTG
> USB PHY > USB 2.0 PHY 
Cell Name Descriptions Type Process Gradation Literature
FZUSB299HH0L USB 2.0 PHY,crystal-less option; UMC 40nm LP/RVT process. Analog_IP 40nm Silver Minus
 
Interface Solution > USB/OTG
> USB PHY > USB 3.0 Crystal-less PHY 
Cell Name Descriptions Type Process Gradation Literature
FZUSB399HH0L Crystal-less USB 3.0 PHY ; UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT Process Analog_IP 40nm Silver Minus
 
Interface Solution > USB/OTG
> USB PHY > USB 3.0 OTG PHY 
Cell Name Descriptions Type Process Gradation Literature
FZOTG300HH0L USB 3.0 PHY ; UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT Process Analog_IP 40nm Silver
FZOTGC300HH0L USB 3.1 Gen.1 TYPE-C PHY ; UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT Process Analog_IP 40nm Contact Sales