Logic Libraries

Updated On:2018-01-20
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Logic Libraries > PowerSlash Core Cell Library
> 9-Track 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_AHS_POWERSLASH
_CORE
UMC 40nm LP/HVT LowK Logic Process 9-track Power Slash Cell Library Library_Group 40nm Bronze
FSH0L_ALS_POWERSLASH
_CORE
UMC 40nm LP/LVT LowK Logic Process 9-track Power Slash Cell Library Library_Group 40nm Bronze
FSH0L_ARS_POWERSLASH
_CORE
UMC 40nm LP/RVT LowK Logic Process 9-track Power Slash Cell Library Library_Group 40nm Bronze
 
Logic Libraries > PowerSlash Core Cell Library
> 9-Track > 9T HVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_BHS_POWERSLASH
_CORE
UMC 40nm LP/HVT Logic Process 9-Track Standard Cell Library (PowerSlash Core) Library_Group 40nm Silver
FSH0L_XHS_POWERSLASH
_CORE
UMC 40nm LP/HVT Logic Process SYNS-like 9T POWERSLASH Cell Library Library_Group 40nm Contact Sales
 
 
Logic Libraries > PowerSlash Core Cell Library
> 9-Track > 9T LVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_BLS_POWERSLASH
_CORE
UMC 40nm LP/LVT Logic Process 9-Track Standard Cell Library (PowerSlash Core) Library_Group 40nm Silver
FSH0L_XLS_POWERSLASH
_CORE
UMC 40nm LP/LVT Logic Process SYNS-like 9T POWERSLASH Cell Library Library_Group 40nm Contact Sales
 
 
Logic Libraries > PowerSlash Core Cell Library
> 9-Track > 9T RVT PSK Library 
Cell Name Descriptions Type Process Gradation Literature
FSH0L_BRS_POWERSLASH
_CORE
UMC 40nm LP/RVT Logic Process 9-Track Standard Cell Library (PowerSlash Core) Library_Group 40nm Silver
FSH0L_XRS_POWERSLASH
_CORE
UMC 40nm LP/RVT Logic Process SYNS-like 9T POWERSLASH Cell Library Library_Group 40nm Contact Sales